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Appendix A
Model 35601A
Table A-1. Latches and Latch bits for Controlling the -hp- 35601A Locally
"SWITCH"
Function
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
S1
S2
S3
S4
S5
S6
S7
S8
FO
F1
F3
LO
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
I
L12
Loaded
Latch
(SW3)
( 8 7 6 5 4 3 2 1 )
OXXX0010
OXXX0001
OXXX0001
OXXX0001
oxxxoooo
oxxxoooo
oxxxoooo
OXXX0100
OXXX0100
OXXX0100
OXXX0010
OXXX0010
OXXX0001
OXXX0010
OXXX1001
OXXX0001
oxxxoooo
oxxxoooo
O X X X 0 0 1 0
O X X X 0 0 1 0
O X X X 0 0 1 1
O X X X 0 0 1 1
O X X X 1 0 0 0
O X X X 1 0 0 1
O X X X 1 0 0 0
O X X X 1 0 0 1
or
O X X X 1 0 0 0
O X X X 1 0 0 1
O X X X 1 0 0 0
O X X X 1 0 0 1
O X X X 1 0 0 1
O X X X 1 0 0 0
O X X X 1 0 0 0
O X X X 0 1 1 1
O X X X 0 1 1 1
O X X X 1 0 0 1
O X X X 0 1 1 1
O X X X 1 0 0 1
O X X X 0 1 1 1
O X X X 0 1 1 1
O X X X 0 1 1 1
j O X X X 1 0 0 0
O X X X 1 0 0 1
*Loaded
Latch
Bits
(SW3)
(87654321)
1 xxxxAxx
1 xAxxxxx
1xxxxx Ax
1xxxxxAx
1 xxAxxxx
1 xxxxAxx
1 Axxxxxx
1 Axxxxxx
1 Axxxxxx
1 xxxxAxx
1 Axxxxxx
1 xxAxxxx
1 xxxAxxx
1 Axxxxxx
1 xAxxxxx
1xxxxxxA
1 xxxAxxx
1 xAxxxxx
1 xAxxxxx
1xxxxxAx
1xxxxxxA
1 xxxxAxx
1xOxxxxx
1xxxOxxx
1xOxxxxx
1 XXX1 XXX
|
1x1xxxxx
1xxxOxxx
1x1xxxxx
1 X X X 1 XXX
1 xxxxAxx
1 xxAxxxx
1 Axxxxxx
1 xxAxxxx
1xxxxxxA
1 xxAxxxx
1 xxxAxxx
1xxxxxxA
1xxxxxAx
1 xAxxxxx
1 xxxxAxx
1 xxxxAxx
1xxxxxAx
Latch
Ref.
Desig.
(A1 board)
U11
U5
U5
U5
U12
U12
U12
U10
U10
U10
U11
U11
U5
U11
U1
U5
U12
U12
U11
U11
U4
U4
U8
U1
U 8
U1
U8
U1
U 8
U1
U1
U8
U8
U9
U9
U1
U9
U1
U9
U9
U9
U8
; m
"SWITCH"
Function
L13
L14
L15
L16
L17
L18
L19
L20
L21
DAC Bits
0
1
2
3
4
5
6
7
positive
negative
GAIN1 Bits
0
1
2
GAIN2 Bits
0
1
2
LEAD LAG Bits
0
1
2
ATTEN1 Bits
0
1
2
3
A T T E N 2 Bits
0
Loaded
Latch
(SW3)
OXXX1000
OXXX1000
OXXX1000
OXXX0111
OXXX0110
OXXX0110
oxxxoooo
oxxxoooo
O X X X 0 0 1 1
O X X X 0 1 0 1
O X X X 0 1 0 0
O X X X 0 1 0 0
O X X X 0 1 0 0
O X X X 0 1 0 1
O X X X 0 1 0 1
O X X X 0 1 0 1
O X X X 0 1 0 1
O X X X 0 0 1 1
O X X X 0 1 0 0
O X X X 0 1 0 1
O X X X 0 1 0 1
O X X X 0 1 1 0
O X X X 0 1 1 0
O X X X 0 1 1 0
O X X X 0 1 1 0
O X X X 0 0 1 1
O X X X 0 1 1 0
O X X X 1 0 0 1
O X X X 0 0 0 1
O X X X 0 0 1 0
O X X X 0 0 0 1
O X X X 0 0 0 1
OXXXOQ11
•Loaded
Latch
Bits
(SW3)
1 xxxAxxx
1xxxxxxA
1xxxxxAx
1 Axxxxxx
1 Axxxxxx
1 xAxxxxx
1xxxxxxA
1xxxxxAx
1xxxxxAx
1xxxxxxA
1 xxAxxxx
1 xAxxxxx
1 xxxAxxx
1 xxxxAxx
1 xxAxxxx
1 xxxAxxx
1xxxxxAx
1 Axxxxxx
1xxxxxAx
1 Axxxxxx
|
1 xAxxxxx
1 xxxxxAx
1xxxxxxA
1 xxxAxxx
1 xxxxAxx
1 xAxxxxx
1 xxAxxxx
1 xxxxAxx
1 Axxxxxx
1 xxxAxxx
1 xxAxxxx
1 xxxxAxx
1 xxxAxxx
Latch
Ref.
Oesig.
(A1 board)
U8
I
U8
U8
U9
U2
U2
U12
U12
U4
U3
U10
U10
U10
U3
U3
U3
U3
U4
U10
U3
U3
U2
U2
U2
U2
U4
U2
U2
U5
U11
U5
U5
U 4
j
• T h e x's in this column are not " d o n ' t care" states; these states should correspond to the previous states of the latch.
(i.e. Every bit in a latch must be entered again even if only one bit is being changed.) The A's may be either 1 or 0 ; in the
turn-on state, all A ' s are 0 .
A-2
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