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Epson S1C6S3N2 Technical Manual

Cmos 4-bit single chip microcomputer
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MF859 - 06
CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER
S1C6S3N2
Technical Manual
S1C6S3N2 Technical Hardware/S1C6S3N2 Technical Software

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Summary of Contents for Epson S1C6S3N2

  • Page 1 MF859 - 06 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C6S3N2 Technical Manual S1C6S3N2 Technical Hardware/S1C6S3N2 Technical Software...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 This manual is individualy described about the hardware and the software of the S1C6S3N2. I. S1C6S3N2 Technical Hardware This part explains the function of the S1C6S3N2, the circuit configu- rations, and details the controlling method. II. S1C6S3N2 Technical Software This part explains the programming method of the S1C6S3N2.
  • Page 5 The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.
  • Page 7 S1C6S3N2 Technical Hardware...

  • Page 9: Table Of Contents

    CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION ...... I-16 Memory Map ..............I-16 Resetting Watchdog Timer ..........I-24 Configuration of watchdog timer ......I-24 Mask option ............I-24 Control of watchdog timer ........I-25 Programming note ........... I-25 EPSON S1C6S3N2 TECHNICAL HARDWARE...
  • Page 10 Mask option (segment allocation) ......I-57 Control of LCD driver ..........I-59 Programming notes ..........I-60 Clock Timer ..............I-61 Configuration of clock timer ........I-61 Interrupt function ........... I-62 Control of clock timer ..........I-63 Programming notes ..........I-65 EPSON I-ii S1C6S3N2 TECHNICAL HARDWARE...
  • Page 11 Programing notes ............ I-86 4.13 Interrupt and HALT ............I-88 Interrupt factors ............I-90 Specific masks and factor flags for interrupt .... I-91 Interrupt vectors ............. I-92 Control of interrupt and HALT ......... I-93 Programming notes ..........I-96 EPSON S1C6S3N2 TECHNICAL HARDWARE I-iii...
  • Page 12 Oscillation Characteristics ..........I-119 CHAPTER 8 PACKAGE ..............I-124 Plastic Package ............. I-124 Ceramic Package for Test Samples ......I-126 CHAPTER 9 PAD LAYOUT ..............I-127 Diagram of Pad Layout ..........I-127 Pad Coordinates ............I-128 EPSON I-iv S1C6S3N2 TECHNICAL HARDWARE...

  • Page 13: Chapter 1 Overview

    Furthermore, the S1C6S3N2 is a shrunk model of the S1C62N32. It can be used as various controller applications such as a clock, game and pager.

  • Page 14: 1.2 Features

    80-pin QFP (plastic) or chip *1 Selected by mask option *2 The supply voltage range of the S1C6S3N2 and S1C6S3A2 is 2.2 to 3.6 V when an LCD panel is used. In this manual, BLD and SVD (supply voltage detection) have the same meaning.

  • Page 15: Block Diagram

    Generator 144 x 4 COM0 K00–K03, K10 I Port COM3 TEST Driver SEG0 P00–P03 SEG37 I/O Port P10–P13 R00–R03 O Port Power R10–R13 Controller AMPP Comparator AMPM Timer Event Stop Fig. 1.3.1 Counter Watch Block diagram EPSON S1C6S3N2 TECHNICAL HARDWARE...

  • Page 16: Pin Layout Diagram

    OSC1 SEG8 SEG27 SEG9 SEG28 SEG10 SEG29 SEG11 SEG30 SEG12 SEG31 N.C. SEG13 SEG32 SEG14 SEG33 SEG15 SEG34 COM3 SEG16 SEG35 Fig. 1.4.1(b) COM2 SEG17 SEG36 Pin layout diagram COM1 TEST SEG37 N.C. : No connection EPSON S1C6S3N2 TECHNICAL HARDWARE...

  • Page 17: 1.5 Pin Description

    Initial setting input terminal TEST Test input terminal *1 6S3N2/6S3L2/6S3B2: Not connected 6S3A2: CR or ceramic oscillation input terminal (Switchable through mask option.) *2 6S3N2/6S3L2/6S3B2: Not connected 6S3A2: CR or ceramic oscillation output terminal (Switchable through mask option.) EPSON S1C6S3N2 TECHNICAL HARDWARE...

  • Page 18: Chapter 2 Power Supply And Initial Reset

    > for oscillators, <V > for LCDs) and the voltage booster circuit (<V > for LCDs). Or the S1C6S3N2 Series generates the necessary internal voltage with the regulated voltage circuit (<V > for oscillators, <V > for LCDs) and the voltage booster circuit (<V...
  • Page 19 Oscillation system Oscillation regulated voltage OSC1–4 circuit circuit LCD system regulated voltage circuit LCD system COM0–3 LCD driver voltage circuit booster/reducer SEG0–37 External circuit power supply Fig. 2.1.1(b) Example of configuration of power supply (S1C6S3N2/6S3A2) EPSON S1C6S3N2 TECHNICAL HARDWARE...
  • Page 20 • S1C6S3L2 3 V LCD panel 1/4, 1/3, 1/2 duty, 1/2 bias Fig. 2.1.2 External elements when 1.5 V LCD system regulated Note: V is shorted to V inside the IC. voltage circuit is not used EPSON S1C6S3N2 TECHNICAL HARDWARE...
  • Page 21 3.0 V LCD 1/2 Bias Internal External × × × S1C6S3N2 3.0 V LCD × × × S1C6S3A2 3.0 V LCD × × × S1C6S3L2 3.0 V LCD Combinations that are marked with an "×" cannot be selected. EPSON S1C6S3N2 TECHNICAL HARDWARE...

  • Page 22: Initial Reset

    CHAPTER 2: POWER SUPPLY AND INITIAL RESET Initial Reset To initialize the S1C6S3N2 Series circuits, initial reset must be executed. There are four ways of doing this. Four types of initial reset factors are available, however be sure to use (1) or (2) for resetting because (3) and (4) are auxiliary reset factors.

  • Page 23: Reset Pin (Reset

    If the CPU runs away for some reason, the watchdog timer Watchdog timer will detect this situation and output an initial reset signal. (Auxiliary reset) See "4.2 Resetting Watchdog Timer" for details. EPSON S1C6S3N2 TECHNICAL HARDWARE I-11...

  • Page 24: Oscillation Detection Circuit (Auxiliary Reset

    Undefined Other peripheral circuit *1 See "4.1 Memory Map" Test Terminal (TEST) This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this termi- nal to V EPSON I-12 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 25: Chapter 3 Cpu, Rom, Ram

    CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM The S1C6S3N2 Series employs the core CPU S1C6200A for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family proces- sors using the S1C6200A.

  • Page 26: 3.2 Rom

    The interrupt vector is allocated to page 1, steps 01H–0FH. 0page Program start address 00H step 1page 01H step 2page 3page Interrupt vector area 4page 5page 0FH step 6page 10H step 7page FFH step Fig. 3.2.1 12 bits ROM configuration EPSON I-14 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 27: Ram

    (3) The data memory 000H–00FH is for the register pointers (RP), and is the addressable memory register area. (4) The data memory is split into two areas, 000H–06FH and 080H–09FH, so take care when allocating the data. (See "4.1 Memory Map" for details.) EPSON S1C6S3N2 TECHNICAL HARDWARE I-15...

  • Page 28: Chapter 4 Peripheral Circuits And Operation

    CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C6S3N2 Series are memory mapped, and interfaced with the CPU. Thus, all the peripheral circuits can be controlled by using the memory operation command to access the I/O data memory in the memory map.
  • Page 29 (3) Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. EPSON S1C6S3N2 TECHNICAL HARDWARE I-17...
  • Page 30 Input port (K00–K03) – High – High *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON I-18 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 31 – High Input port (K10) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-19...
  • Page 32 Output port (R00–R03) High High *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON I-20 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 33 Timer data (watchdog timer 1 Hz) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-21...
  • Page 34 High order (EV04–EV07) EV05 EV04 *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON I-22 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 35 I/O control register 1 (P10–P13) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-23...

  • Page 36: Resetting Watchdog Timer

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) Resetting Watchdog Timer Configuration of The S1C6S3N2 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU.

  • Page 37: Control Of Watchdog Timer

    This bit is dedicated for writing, and is always "0" for read- out. Programming note When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0–WD2) cannot be used for timer applications. EPSON S1C6S3N2 TECHNICAL HARDWARE I-25...

  • Page 38: Oscillation Circuit

    (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (C ) between terminals OSC1 and V OSC3 oscillation In the S1C6S3N2 Series, the S1C6S3A2 has twin clock specification. The mask option enables selection of either circuit the CR or ceramic oscillation circuit (OSC3 oscillation cir- cuit) as the CPU's subclock.
  • Page 39 ) located between terminals OSC3 and OSC4 and V For both C and C , connect capacitors that are about 100 pF. To lower current consumption of the OSC3 oscilla- tion circuit, oscillation can be stopped through the software. EPSON S1C6S3N2 TECHNICAL HARDWARE I-27...

  • Page 40: Configuration Of Oscillation Circuit

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit) The S1C6S3N2, 6S3L2 and 6S3B2 have one oscillation Configuration of circuit (OSC1), and the S1C6S3A2 has two oscillation oscillation circuit circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and pe- ripheral circuits.

  • Page 41: Control Of Oscillation Circuit

    When it is necessary to operate the CPU of the S1C6S3A2 at high speed, set OSCC to "1". At other times, set it to "0" to lessen the current consumption. For the S1C6S3N2, 6S3L2 and 6S3B2, keep OSCC set to "0". At initial reset, OSCC is set to "0".

  • Page 42: Programming Notes

    (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. EPSON I-30 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 43: Input Ports (K00-K03, K10

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) Input Ports (K00–K03, K10) The S1C6S3N2 Series has five bits general-purpose input Configuration of ports. Each of the input port terminals (K00–K03, K10) input ports provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option.

  • Page 44: Differential Registers And Interrupt Function

    Interrupt for K10 can be gener- ated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.3 shows an example of an interrupt for K00–K03. EPSON I-32 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 45 Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt genera- tion. EPSON S1C6S3N2 TECHNICAL HARDWARE I-33...

  • Page 46: Mask Option

    When "Use" is selected, a maximum delay of 1 ms occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1". EPSON I-34 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 47: Control Of Input Ports

    Interrupt factor flag SWIT0 (stopwatch 10 Hz) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-35...
  • Page 48 When "0" is written : Mask Read-out : Valid With these registers, masking of the input port bits can be selected for each of the five bits. At initial reset, these registers are all set to "0". EPSON I-36 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 49: Programming Notes

    (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. EPSON S1C6S3N2 TECHNICAL HARDWARE I-37...
  • Page 50 (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (High status). EPSON I-38 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 51 "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON S1C6S3N2 TECHNICAL HARDWARE I-39...

  • Page 52: Output Ports (R00-R03, R10-R13

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) Output Ports (R00–R03, R10–R13) Configuration of The S1C6S3N2 Series has general output ports (4 bits x 2). Output specifications of the output ports can be selected output ports individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output.
  • Page 53 Special output BZ (Only when R10 = BZ output is selected) FOUT Register (R10) Register (R13) (Without SW) Register (R11) FOUT Register (R12 ) Address Mask option (07CH) Fig. 4.5.2 Structure of output port R10–R13 EPSON S1C6S3N2 TECHNICAL HARDWARE I-41...
  • Page 54 OSC1 16,384 OSC1 8,192 OSC1 4,096 OSC1 / 16 2,048 OSC1 / 32 1,024 OSC1 / 64 OSC1 / 128 OSC1 Note A hazard may occur when the FOUT signal is turned ON or OFF. EPSON I-42 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 55: Control Of Output Ports

    When "1" is written in the register, the output port terminal goes high (V ), and when "0" is written, the output port terminal goes low (V At initial reset, all registers are set to "0". EPSON S1C6S3N2 TECHNICAL HARDWARE I-43...
  • Page 56 When "1" is written to register BZFQ, the frequency of the buzzer signal is set in 2 kHz, and in 4 kHz when "0" is written. At initial reset, BZFQ is set to "0" (4 kHz). EPSON I-44 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 57: Programming Note

    At initial reset, this register is set to "0". When BZ, BZ and FOUT are selected with the mask option, Programming note a hazard may be observed in the output waveform when the data of the output register changes. EPSON S1C6S3N2 TECHNICAL HARDWARE I-45...

  • Page 58: I/O Ports (P00-P03, P10-P13

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) I/O Ports (P00–P03, P10–P13) Configuration of The S1C6S3N2 Series has general-purpose I/O ports (4 bits x 2). Figure 4.6.1 shows the configuration of the I/O ports. I/O ports The four bits of each of the I/O ports P00–P03 and P10–P13 can be set to either input mode or output mode.

  • Page 59: I/O Control Register And I/O Mode

    Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port. EPSON S1C6S3N2 TECHNICAL HARDWARE I-47...

  • Page 60: Control Of I/O Ports

    I/O control register 1 (P10–P13) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON I-48 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 61 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs. EPSON S1C6S3N2 TECHNICAL HARDWARE I-49...

  • Page 62: Programming Notes

    Because of this, if a low- impedance load is connected and read-out performed, the value of the register and the read-out result may differ. EPSON I-50 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 63: Lcd Driver (Com0-3, Seg0-37

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD Driver (COM0–3, SEG0–37) Configuration of LCD The S1C6S3N2 Series has four common terminals and 38 segment terminals, so that it can drive an LCD with a maxi- driver mum of 152 (38 x 4) segments.
  • Page 64 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD lighting status COM0 COM0 COM1 COM2 COM1 COM3 SEG0–37 COM2 Not lit COM3 0–37 Fig. 4.7.1 Frame frequency Drive waveform for 1/4 duty (1/3 bias) EPSON I-52 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 65 Fig. 4.7.2 Frame frequency Drive waveform for 1/3 duty (1/3 bias) LCD lighting status COM0 COM0 COM1 COM1 SEG0–37 COM2 Not lit COM3 0–37 Fig. 4.7.3 Frame frequency Drive waveform for 1/2 duty (1/3 bias) EPSON S1C6S3N2 TECHNICAL HARDWARE I-53...
  • Page 66 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) LCD lighting status COM0 COM0 L1,L2 COM1 COM2 COM1 COM3 SEG0–37 COM2 Not lit COM3 L1,L2 0–37 Fig. 4.7.4 Frame frequency Drive waveform for 1/4 duty (1/2 bias) EPSON I-54 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 67 Frame frequency Drive waveform for 1/3 duty (1/2 bias) LCD lighting status COM0 COM0 L1,L2 COM1 COM1 SEG0–37 COM2 Not lit COM3 L1,L2 0–37 Fig. 4.7.6 Frame frequency Drive waveform for 1/2 duty (1/2 bias) EPSON S1C6S3N2 TECHNICAL HARDWARE I-55...

  • Page 68: Switching Between Dynamic And All Off

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) The S1C6S3N2 Series provides software setting of the LCD Switching between ALL OFF. This function enables easy ALL OFF of the LCD dynamic and ALL panel. (COM and SEG terminals output a constant voltage.)

  • Page 69: Mask Option (Segment Allocation

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (LCD Driver) Mask option (1) Segment allocation (segment allocation) As shown in Figure 4.1.2, segment data of the S1C6S3N2 Series is decided depending on display data written to the segment data memory (write-only) at address 40H–6FH or C0H–EFH.
  • Page 70 Pch open drain output can be selected for each pin with the mask option. Note The pin pairs are the combination of SEG2*n and SEG2*n + 1 (where n is an integer from 0 to 18). EPSON I-58 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 71: Control Of Lcd Driver

    *5 Constantly "0" when being read Address Page High 4 or C Segment data memory (38 words x 4 bits) 5 or D 40H–6FH = R/W C0H–EFH = W 6 or E Fig. 4.7.8 Segment data memory map EPSON S1C6S3N2 TECHNICAL HARDWARE I-59...

  • Page 72: Programming Notes

    CPU). Initialize the segment data memory by executing initial processing. (2) When C0H–EFH is selected for the segment data memory, that area becomes write-only. Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). EPSON I-60 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 73: Clock Timer

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Clock Timer) Clock Timer Configuration of The S1C6S3N2 Series has a built-in clock timer as the source oscillator for OSC1 (crystal oscillator). The clock clock timer timer is configured of a seven-bit binary counter that serves as the input clock, a 256 kHz signal output by the prescaler.

  • Page 74: Interrupt Function

    (ETI32, ETI8, ETI2). However, regardless of the interrupt mask register setting, the interrupt factor flag is set to "1" at the falling edge of the corresponding signal. EPSON I-62 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 75: Control Of Clock Timer

    I/O control register 0 (P00–P03) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-63...
  • Page 76 Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0". EPSON I-64 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 77: Programming Notes

    "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON S1C6S3N2 TECHNICAL HARDWARE I-65...

  • Page 78: Stopwatch Counter

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Stopwatch Counter) Stopwatch Counter Configuration of The S1C6S3N2 Series incorporates a 1/100 sec and 1/10 sec stopwatch counter. The stopwatch counter is configured stopwatch counter of a two-stage, four-bit BCD counter serving as the input...

  • Page 79: Count-Up Pattern

    25/256 sec and 26/256 sec intervals in the ratio of 4:6, to generate a 1 Hz signal. The count-up intervals are 25/ 256 sec and 26/256 sec, which do not amount to an accu- rate 1/10 sec. EPSON S1C6S3N2 TECHNICAL HARDWARE I-67...

  • Page 80: Interrupt Function

    The respective interrupts can be masked separately through the interrupt mask registers (EISWIT0, EISWIT1). However, regardless of the setting of the interrupt mask registers, the interrupt factor flags are set to "1" by the overflow of their corresponding counters. EPSON I-68 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 81: Control Of Stopwatch Counter

    I/O control register 0 (P00–P03) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-69...
  • Page 82 Be very careful when interrupt factor flags are in the same address. At initial reset, these flags are set to "0". EPSON I-70 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 83 STOP status, and then return to the RUN status. Also, the duration of the STOP status must be within 976 µs (256 Hz 1/4 cycle). At initial reset, this register is set to "0". EPSON S1C6S3N2 TECHNICAL HARDWARE I-71...

  • Page 84: Programming Notes

    "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON I-72 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 85: Event Counter

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Event Counter) 4.10 Event Counter Configuration of The S1C6S3N2 Series has an event counter that counts the clock signals input from outside. event counter The event counter is configured of eight-bit binary counters (UP counters). The clock pulses are input through K10 pin or K03 pin of the input port.
  • Page 86 Table 4.10.1 lists the defined time depending on the fre- quency selected. Table 4.10.1 Selection /128 OSC1 OSC1 Defined time depending 0.74 5.86 on frequency selected 0.49 3.91 0.24 1.95 0.25 1.96 (Unit: msec) = 32.768 kHz OSC1 Max value Others : Min value EPSON I-74 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 87: Control Of Event Counter

    The four high-order data bits of event counter are read out. EV04–EV07: Event counter High-order These four bits are read-only, and cannot be used for writ- (0F9H) ing. At initial reset, this counter is set to "0H". EPSON S1C6S3N2 TECHNICAL HARDWARE I-75...

  • Page 88: Programming Note

    At initial reset, this register is set to "0". Programming note To prevent erroneous reading of the event counter data, read out the counter data several times, compare it, and use the matching data as the result. EPSON I-76 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 89: Analog Comparator

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Analog Comparator) 4.11 Analog Comparator The S1C6S3N2 Series incorporates an MOS input analog Configuration of comparator. This analog comparator, which has two differ- analog comparator ential input terminals (inverted input terminal AMPM, noninverted input terminal AMPP), can be used for general purposes.

  • Page 90: Control Of Analog Comparator

    AMPDT is "0" when the input level of the inverted input terminal (AMPM) is greater than the input level of the noninverted input terminal (AMPP); and "1" when smaller. At initial reset, AMPDT is set to "1". EPSON I-78 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 91: Programming Notes

    OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 ms for the operation of the analog comparator to stabilize before reading the output data of the analog cpmparator from AMPDT. EPSON S1C6S3N2 TECHNICAL HARDWARE I-79...

  • Page 92: Supply Voltage Detection (Svd) Circuit And Heavy Load Protection Function

    Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function Configuration of The S1C6S3N2 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source SVD circuit voltage lowers. The configuration of the SVD circuit is shown in Figure 4.12.1.

  • Page 93: Heavy Load Protection Function

    ON time to 10 msec per second of opera- tion time. (2) In case of S1C6S3N2/6S3A2 The S1C6S3N2/6S3A2 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights.

  • Page 94: Detection Timing Of Svd Circuit

    S1C6S3A2, the OSC3 detection result at the timing in above may be invalid or incorrect. (When performing SVD detection using the timing in , be sure that the CPU system clock is f OSC1 EPSON I-82 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 95 However, when a crystal oscillation clock (f ) is se- OSC1 lected for the CPU system clock in S1C6S3N2, S1C6S3L2, S1C6S3B2 and S1C6S3A2, the instruction cycles are long enough, so that there is no need for concern about maintaining 100 µs for the BLS = "1" with the software.

  • Page 96: Control Of Svd Circuit

    SVD circuit ON time. There are two types of sampling time, as follows: (1) Sampling at time of one instruction cycle immediately after HLMOD = "1" (2) Sampling at cycles of 2 Hz output by the clock timer while HLMOD = "1" EPSON I-84 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 97 BLS is reset to "0" the detection result is loaded to the SVD latch. To obtain a stable SVD detection result, the SVD circuit must be set to ON with at least 100 µs. Hence, to obtain the SVD detection result, follow the programming sequence below. EPSON S1C6S3N2 TECHNICAL HARDWARE I-85...

  • Page 98: Programing Notes

    However, when a crystal oscillation clock (f ) is selected OSC1 for the CPU system clock in S1C6S3N2, S1C6S3L2, S1C6S3B2 and S1C6S3A2, the instruction cycles are long enough, so that there is no need for concern about main- taining 100 µs for the BLS = "1" with the software.
  • Page 99 OFF (at least 100 µs is necessary for the ON status) and then return to the normal mode. The S1C6S3N2/6S3A2 returns to the normal mode after driving a heavy load without special software processing. (4) When the BLS is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 msec per second of operation time.

  • Page 100: 4.13 Interrupt And Halt

    CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Interrupt and HALT) 4.13 Interrupt and HALT The S1C6S3N2 Series provides the following interrupt set- tings, each of which is maskable. External interrupt : Input interrupt (two) Internal interrupt : Timer interrupt (three) Stopwatch interrupt (two) To authorize interrupt, the interrupt flag must be set to "1"...
  • Page 101 Program counter ETI8 (four low-order bits) TI32 ETI32 (LSB) DFK00 EIK00 (interrupt request) DFK01 EIK01 DFK02 EIK02 DFK03 EIK03 DFK10 EIK10 Interrupt factor flag Interrupt mask register Differential register Fig. 4.13.1 Configuration of interrupt circuit EPSON S1C6S3N2 TECHNICAL HARDWARE I-89...

  • Page 102: Interrupt Factors

    Clock timer 32 Hz falling edge TI32 (079H·D0) Stopwatch counter SWIT1 1 Hz falling edge (07AH·D1) Stopwatch counter SWIT0 10 Hz falling edge (07AH·D0) Input data (K00–K03) Rising or falling edge (07AH·D2) Input data (K10) Rising or falling edge (07AH·D3) EPSON I-90 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 103: Specific Masks And Factor Flags For Interrupt

    (079H·D0) EISWIT1 (076H·D1) SWIT1 (07AH·D1) EISWIT0 (076H·D0) SWIT0 (07AH·D0) EIK03 (075H·D3) EIK02 (075H·D2) (07AH·D2) EIK01 (075H·D1) EIK00 (075H·D0) EIK10 (077H·D2) (07AH·D3) * There is an interrupt mask register for each pin of the input ports. EPSON S1C6S3N2 TECHNICAL HARDWARE I-91...

  • Page 104: Interrupt Vectors

    Masked PCS2 Timer interrupt Enabled Masked PCS1 Input (K00–K03) interrupt Enabled Masked PCS0 Input (K10) interrupt or Enabled Masked The four low-order bits of the program counter are indirectly addressed through the interrupt request. EPSON I-92 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 105: Control Of Interrupt And Halt

    – High Input port (K10) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL HARDWARE I-93...
  • Page 106 Interrupt factor flag SWIT0 (stopwatch 10 Hz) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON I-94 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 107 – EIK00–EIK03: Interrupt mask registers (075H) – IK0: Interrupt factor flag (07AH·D2) See "Control of input ports". – DFK10: Differential register (077H·D1) – EIK10: Interrupt mask register (077H·D2) – IK1: Interrupt factor flag (07AH·D3) See "Control of input ports". EPSON S1C6S3N2 TECHNICAL HARDWARE I-95...

  • Page 108: Programming Notes

    "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON I-96 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 109: Chapter 5 Summary Of Notes

    CHAPTER 5 SUMMARY OF NOTES Notes for Low Current Consumption The S1C6S3N2 Series contains control registers for each of the circuits so that current consumption can be lowered. These control registers lower the current consumption through programs that operate the circuits at the minimum levels.

  • Page 110: Summary Of Notes By Function

    Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configura- tion. Aim for a wait time of about 1 ms. EPSON I-98 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 111 Low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. EPSON S1C6S3N2 TECHNICAL HARDWARE I-99...
  • Page 112 (1) When 40H–6FH is selected for the segment data memory, LCD driver the memory data and the display will not match until the area is initialized (through, for instance, memory clear processing by the CPU). Initialize the segment data memory by executing initial processing. EPSON I-100 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 113 OFF when it is not necessary. (2) After setting AMPON to "1", wait at least 3 ms for the operation of the analog comparator to stabilize before reading the output data of the analog cpmparator from AMPDT. EPSON S1C6S3N2 TECHNICAL HARDWARE I-101...
  • Page 114 (4) When the BLS is to be turned on during operation in the heavy load protection mode, limit the ON time to 10 milliseconds per second of operation time. EPSON I-102 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 115 "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON S1C6S3N2 TECHNICAL HARDWARE I-103...

  • Page 116: Diagram Of Basic External Connections

    32.768 kHz, CI = 35 kΩ Trimmer capacitor 5–25 pF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF Note The above table is simply an example, and is not guaranteed to work. EPSON I-104 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 117 Drain capacitance 100 pF Resistance for CR oscillation 33 kΩ 0.1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF 3.3 µF Note The above table is simply an example, and is not guaranteed to work. EPSON S1C6S3N2 TECHNICAL HARDWARE I-105...
  • Page 118 S1C6S3N2 Series (BZ) (BZ) Piezo Protection resistance 100 Ω Protection resistance 100 Ω When driving the buzzer, set the IC into the heavy load protection mode since the supply voltage changes according to the buzzer frequency. EPSON I-106 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 119: Chapter 7 Electrical Characteristics

    260°C, 10 sec (lead section) – Permitted loss *1 For 80-pin plastic package *2 The permissible total output current is the sum total of the current (average current) that simultaneously flows from the output pins (or is drawn in). EPSON S1C6S3N2 TECHNICAL HARDWARE I-107...

  • Page 120: 7.2 Recommended Operating Conditions

    Note, however, that the ON time for BLS in the heavy load protection must be limited to 10 milliseconds per second of operation time. *2 The possibility of LCD panel display differs depending on the characteristics of the LCD panel. *3 2.2 V for applications that use LCD display. EPSON I-108 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 121: 7.3 Dc Characteristics

    = -0.05V COM0–COM3 µA output current µA +0.05V Segment output current I = -0.05V SEG0–SEG37 µA (at LCD output) µA +0.05V Segment output current I = 0.1·V SEG0–SEG37 -200 µA (at DC output) = 0.9·V µA EPSON S1C6S3N2 TECHNICAL HARDWARE I-109...
  • Page 122 = -0.05V COM0–COM3 µA output current µA +0.05V Segment output current I = -0.05V SEG0–SEG37 µA (at LCD output) µA +0.05V Segment output current I = 0.1·V SEG0–SEG37 -100 µA (at DC output) = 0.9·V µA EPSON I-110 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 123: 7.4 Analog Circuit Characteristics And Consumed Current

    CHAPTER 7: ELECTRICAL CHARACTERISTICS 7.4 Analog Circuit Characteristics and Consumed Current S1C6S3N2 (Normal mode) =0V, V =-3.0V, f =32.768kHz, C =25pF, Ta=25°C, V OSC1 internal voltage, C1=C2=C3=C4=C5=0.1µF) Item Code Condition Min. Typ. Max. Unit 1/2·V 1/2·V Internal voltage Connects a 1MΩ load resistance ×...
  • Page 124 CHAPTER 7: ELECTRICAL CHARACTERISTICS S1C6S3N2 (Heavy load protection mode) =0V, V =-3.0V, f =32.768kHz, C =25pF, Ta=25°C, V OSC1 internal voltage, C1=C2=C3=C4=C5=0.1µF) Item Code Condition Min. Typ. Max. Unit 1/2·V 1/2·V Internal voltage Connects a 1MΩ load resistance × 0.9 -0.1...
  • Page 125 Inverted input (AMPM) Analog comparator offset voltage Analog comparator 1.1V response time ±30mV 0.65 µA Consumed current During HALT No panel load µA During operation *1 The SVD circuit and analog comparator are in the OFF status. EPSON S1C6S3N2 TECHNICAL HARDWARE I-113...
  • Page 126 34.0 µA Consumed current During HALT No panel load 14.5 40.0 µA During operation *1 The SVD circuit is on status (HLMOD = "1", BLS = "0"). The analog comparator is in the OFF status. EPSON I-114 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 127 Inverted input (AMPM) Analog comparator offset voltage Analog comparator 1.1V response time ±30mV 0.65 µA Consumed current During HALT No panel load µA During operation *1 The SVD circuit and analog comparator are in the OFF status. EPSON S1C6S3N2 TECHNICAL HARDWARE I-115...
  • Page 128 34.0 µA Consumed current During HALT No panel load 14.5 40.0 µA During operation *1 The SVD circuit is on status (HLMOD = "1", BLS = "0"). The analog comparator is in the OFF status. EPSON I-116 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 129 µA Consumed current During HALT No panel load µA During operation OSCC = "0" µA During operation No panel load at 1 MHz *1 The SVD circuit and analog comparator are in the OFF status. EPSON S1C6S3N2 TECHNICAL HARDWARE I-117...
  • Page 130 During operation OSCC = "0" µA During operation No panel load at 1 MHz *1 The SVD circuit is on status (HLMOD = "1", BLS = "0"). The analog comparator is in the OFF status. EPSON I-118 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 131: 7.5 Oscillation Characteristics

    Including incidental (drain) capacitance inside IC Frequency/voltage = -1.8 to -3.6V deviation Frequency/IC f/IC deviation Frequency adjustment = 5 to 25pF range Harmonic oscillation -3.6 start voltage Permitted leak Between OSC1 MΩ leak resistance and V EPSON S1C6S3N2 TECHNICAL HARDWARE I-119...
  • Page 132 MΩ leak resistance and V *1 Parentheses indicate value for operation in heavy load protection mode. Note, however, that the ON time for BLS must be limited to 10 milliseconds per second of operation time. EPSON I-120 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 133 MΩ leak resistance and V *1 Parentheses indicate value for operation in heavy load protection mode. Note, however, that the ON time for BLS must be limited to 10 milliseconds per second of operation time. EPSON S1C6S3N2 TECHNICAL HARDWARE I-121...
  • Page 134 Including incidental (drain) capacitance inside IC Frequency/voltage = -2.2 to -3.6V deviation Frequency/IC f/IC deviation Frequency adjustment = 5 to 25pF range Harmonic oscillation -3.6 start voltage Permitted leak Between OSC1 MΩ leak resistance and V EPSON I-122 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 135 If no special requirement =0V, V =-3.0V, ceramic oscillation: 1MHz =100pF, Ta=25°C Item Code Condition Min. Typ. Max. Unit Oscillation start voltage Vsta -1.8 Oscillation start time = -2.2 to -3.6V Oscillation stop voltage Vstp -1.8 EPSON S1C6S3N2 TECHNICAL HARDWARE I-123...

  • Page 136: Chapter 8 Package

    CHAPTER 8: PACKAGE CHAPTER 8 PACKAGE Plastic Package QFP5-80pin (Unit: mm) ±0.4 25.6 ±0.1 20.0 Index ±0.1 ±0.1 0.35 0~12° ±0.3 Note The dimensions are subject to change without notice. EPSON I-124 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 137 CHAPTER 8: PACKAGE QFP14-80pin (Unit: mm) ±0.4 14.0 ±0.1 12.0 Index ±0.1 0.18 ±0.2 Note The dimensions are subject to change without notice. EPSON S1C6S3N2 TECHNICAL HARDWARE I-125...

  • Page 138: 8.2 Ceramic Package For Test Samples

    8.2 Ceramic Package for Test Samples (Unit: mm) ± 0.15 26.8 ± 0.18 20.0 ± 0.05 ± 0.05 0.80 0.35 Grass Note The ceramic package is fixed in this form regardless selecting of the plastic package form. EPSON I-126 S1C6S3N2 TECHNICAL HARDWARE...

  • Page 139: Chapter 9 Pad Layout

    CHAPTER 9: PAD LAYOUT PAD LAYOUT CHAPTER 9 Diagram of Pad Layout (0,0) Die No. 3.29 mm Chip thickness: 400 µm Pad opening: 95 µm EPSON S1C6S3N2 TECHNICAL HARDWARE I-127...

  • Page 140: 9.2 Pad Coordinates

    78 SEG36 1,478 1,179 25 RESET -1,478 52 SEG11 232 -1,631 79 SEG37 1,478 1,310 26 OSC4 -1,478 53 SEG12 362 -1,631 27 OSC3 -1,478 54 SEG13 492 -1,631 Chip size X : 3,288 Y : 3,593 EPSON I-128 S1C6S3N2 TECHNICAL HARDWARE...
  • Page 141 S1C6S3N2 Technical Software...
  • Page 143 Example of Interrupt Vector Processing ......II-18 Programming Notes ............II-21 CHAPTER 5 PERIPHERAL CIRCUITS ............ II-22 Watchdog Timer ............. II-22 Watchdog timer memory map ........II-22 Example of reset processing for watchdog timer ..II-23 Programming note ........... II-24 EPSON S1C6S3N2 TECHNICAL SOFTWARE II-i...
  • Page 144 Input port memory map .......... II-69 Example of using input ports ........II-71 Programming notes ..........II-80 I/O Ports ................. II-82 I/O port memory map ..........II-82 Example of program for I/O ports ......II-83 Programming notes ..........II-86 EPSON II-ii S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 145 Example of Initialize Program ........II-104 CHAPTER 7 SUMMARY OF NOTES ........... II-106 CHAPTER 8 CPU ................II-113 S1C6S3N2 Restrictions ..........II-113 Instruction Set ............... II-113 APPENDIX • Table of cross assembler pseudo-instructions ....II-119 • Table of ICE commands ............ II-120 EPSON...

  • Page 147: Block Diagram

    144 x 4 COM0 K00–K03, K10 I Port COM3 TEST Driver SEG0 P00–P03 SEG37 I/O Port P10–P13 R00–R03 O Port Power R10–R13 Controller AMPP Comparator AMPM Timer Event Stop Counter Watch Fig. 1.1 Block diagram EPSON S1C6S3N2 TECHNICAL SOFTWARE II-1...

  • Page 148: Chapter 2 Program Memory

    CHAPTER 2: PROGRAM MEMORY CHAPTER 2 PROGRAM MEMORY The S1C6S3N2 Series has a mask ROM of 2,048 steps × 12 bits, for storing programs. Address space for program memory is configured of one bank of 8 pages × 256 steps.

  • Page 149: Programming Notes

    "CALZ", "CALZ" will have priority and data set with "PSET" will be ignored. (6) The program memory can be used as a data table through the table look-up instruction. For details of the instructions, refer to "S1C6200/6200A Core CPU Manual". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-3...

  • Page 150: Chapter 3 Data Memory

    CHAPTER 3: DATA MEMORY CHAPTER 3 DATA MEMORY The S1C6S3N2 Series has a general-purpose RAM (144 words × 4 bits ), I/O memory for controlling the internal peripheral circuits (32 words × 4 bits), and the optionally selectable segment memory (48 words × 4 bits). All these are allocated to the data memory addresses on page 0.

  • Page 151: Ram Map

    (2) Subroutine calls and interrupts take up three words of the stack area. (3) When addresses 40H–6FH have been allocated as seg- ment memory by option selection, 48 words of RAM can be used as segment area. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-5...

  • Page 152: 3.4 I/O Memory Map

    Input port (K00–K03) – High – High *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON II-6 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 153 – High Input port (K10) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL SOFTWARE II-7...
  • Page 154 Output port (R00–R03) High High *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON II-8 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 155 Timer data (watchdog timer 1 Hz) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL SOFTWARE II-9...
  • Page 156 High order (EV04–EV07) EV05 EV04 *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON II-10 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 157 I/O control register 1 (P10–P13) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL SOFTWARE II-11...

  • Page 158: Chapter 4 Interrupt And Halt

    CHAPTER 4: INTERRUPT AND HALT CHAPTER 4 INTERRUPT AND HALT The S1C6S3N2 Series provides the following interrupt set- tings, each of which is maskable. External interrupts: Input interrupts (two) Internal interrupts: Timer interrupt (three channels) Stopwatch interrupt (two channels) When a HALT instruction is input the CPU operating clock stops, and the CPU enters the HALT status.

  • Page 159: 4.1 Control Of Interrupt And Halt

    – High Input port (K10) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON S1C6S3N2 TECHNICAL SOFTWARE II-13...
  • Page 160 Interrupt factor flag SWIT0 (stopwatch 10 Hz) *1 Initial value at the time of initial reset *2 Not set in the circuit *3 Undefined *4 Reset (0) immediately after being read *5 Constantly "0" when being read EPSON II-14 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 161: Generation Of Interrupt

    "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-15...

  • Page 162: Example Of Main Routine: Entering Halt

    DI status. 2. When an interrupt is generated, the DI status (interrupt flag = "0") comes into effect automatically, so the EI instruction is necessary for each loop. EPSON II-16 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 163: Interrupt Vector Map

    Generation of INTK1, TINT and SWINTT Generation of INTK0, TINT and SWINTT Generation of all interrupts Addresses (start addresses of interrupt processing routines) to jump to are written into the addresses available for inter- rupt vector allocation. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-17...

  • Page 164: Example Of Interrupt Vector Processing

    Table 4.5.1 Priority Interrupt Factor Order of interrupt priority in Stopwatch 10 Hz program example Stopwatch 1 Hz K00–K03 input ports K10 input port Clock timer 32 Hz Clock timer 8 Hz Clock timer 2 Hz EPSON II-18 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 165 K0 interrupt processing "IK0" INK1: Y,YIKSTB If the K1 interrupt factor flag is set MY,1000B Z,INTI CALL then execute K1 interrupt processing "IK1" INTI: X,79H Reset and store Y,YETI the timer interrupt factor flags MY,MX in the buffer EPSON S1C6S3N2 TECHNICAL SOFTWARE II-19...
  • Page 166 Addresses of buffers IKSTB and TIB can be set anywhere in RAM. This routine assumes that processing routines "SIT0", "SIT1", "IK0", "IK1", "TI32", "TI8" and "TI2" have been pre- pared separately for each of the interrupts. EPSON II-20 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 167: 4.6 Programming Notes

    "1", an interrupt request will be generated by the interrupt factor flags set timing, or an interrupt request will not be generated. Be very careful when interrupt factor flags are in the same address. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-21...

  • Page 168: Chapter 5 Peripheral Circuits

    CHAPTER 5: PERIPHERAL CIRCUITS (Watchdog Timer) CHAPTER 5 PERIPHERAL CIRCUITS Peripheral circuits of the S1C6S3N2 Series, such as the timer and I/O, are interfaced with the CPU by memory mapped I/O format. This means that all peripheral circuits can be control- led by accessing the memory map's I/O memory or segment memory with memory operation instructions.

  • Page 169: Example Of Reset Processing For Watchdog Timer

    (n+1) sec (n+1).5 sec Time "CK" is executed "CK" is executed Fig. 5.1.1 Watchdog timer Watchdog timer is reset is reset Timing chart EPSON S1C6S3N2 TECHNICAL SOFTWARE II-23...

  • Page 170: Programming Note

    "basic timer 'CK'".) When the watchdog timer is used for the reset function, the Programming note software must reset the watchdog timer within 3 seconds. In this case, timer data (WD0–WD2) cannot be used for timer applications. EPSON II-24 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 171: Osc3

    (S1C6S3A2 only). When "1" is written: OSC3 is selected When "0" is written: OSC1 is selected Read-out: Available This register cannot be controlled for S1C6S3N2/6S3L2/ 6S3B2, so that OSC1 is selected regardless of the set value. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-25...

  • Page 172: Example Of Using Osc3

    Example of using OSC3 Note To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C6S3N2/ 6S3L2/6S3B2, keep OSCC fixed to "0". (1) Switching from OSC1 to OSC3 Specifications This subroutine first sets OSC3 to ON, and then, after about 5 ms, switches the CPU clock to OSC3.

  • Page 173: Programming Notes

    OSC3 oscillation OFF. (3) To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C6S3N2/6S3L2/6S3B2, keep OSCC fixed to "0". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-27...

  • Page 174: Supply Voltage Detection (Svd) Circuit And Heavy Load Protection Function

    CHAPTER 5: PERIPHERAL CIRCUITS (SVD Circuit and Heavy Load Protection Function) Supply Voltage Detection (SVD) Circuit and Heavy Load Protection Function The S1C6S3N2 Series has a built-in supply voltage detection (SVD) circuit, so that the software can find when the source voltage lowers.
  • Page 175 "DSBLD" is executed. n sec n.5 sec (n+1) sec (n+1).5 sec Time "CK" is executed "CK" is executed Fig. 5.3.1 Supply voltage Supply voltage Timing chart is detected is detected EPSON S1C6S3N2 TECHNICAL SOFTWARE II-29...
  • Page 176 (See page 63, "Example of using timer interrupt" for how to make "basic timer 'CK'".) Timing chart of SVD operation Criteria voltage Source voltage (1.2 V) 1 sec BLS register BLD register HLMOD circuit 0.5 sec Fig. 5.3.2 Timing chart of SVD operation SVD circuit EPSON II-30 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 177 BLS is fixed to "0" when the HLMOD is turnd OFF, because BLS risides in the same bits at the same address as BLD, and one or the other is selected by write or read operation. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-31...
  • Page 178 Return to parent routine TI21: MX,XTISF XOR 0FH ; TISF = "1": Reset the TIS flag CALL Execute the basic timer "CK" Return to parent routine Note When the HLMOD is turned OFF, BLS is fixed to "0". EPSON II-32 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 179: Example Of Using Heavy Load Protection Function

    ON time to 10 msec per second of opera- tion time. (2) In case of S1C6S3N2/6S3A2 The S1C6S3N2/6S3A2 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes, such as when an external buzzer sounds or an external lamp lights.
  • Page 180 Return to parent routine This routine assumes that the addresses of the flag set related to heavy load protection functions together with the 0.5-sec flag are allocated suitably in RAM as the addresses of the timing flag set. EPSON II-34 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 181 TISF = "0": Set the TIS flag MX,XHLOFDL If the HLOF flag is set Z,TI2RT MX,XHLOFDL then HLOFDLF = "0" or "1"? NZ,TI2HLO MX,XHLOFDL HLOFDLF = "0": Set the HLOFDL flag Return to parent routine EPSON S1C6S3N2 TECHNICAL SOFTWARE II-35...
  • Page 182 BLS is set ON and OFF, and then the heavy load protection mode is released. HLONBZ:LD X,76H Set the heavy load protection mode MX,1000B X,7CH Switch BZ ON MX,0001B Return to parent routine BZHLOF:LD X,7CH Stop BZ MX,1110B X,76H EPSON II-36 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 183 When the heavy load protection function is selected for the Specifications S1C6S3N2 or S1C6S3A2 by the mask option setting, the "HLBZ10" routine sets the heavy load protection mode and outputs the BZ signal for 10 msec, then, it releases the heavy load protection mode.

  • Page 184: Programming Notes

    2. When detection is done at BLS After writing "1" on BLS, write "0" after at least 100 µs has lapsed (the following instruction can write "0" because the instruction cycle is long enough) and then read the BLD. EPSON II-38 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 185 OFF (at least 100 µs is necessary for the ON status) and then return to the normal mode. The S1C6S3N2/6S3A2 returns to the normal mode after driving a heavy load without special software processing. (5) To reduce current consumption, be careful not to set the heavy load protection mode with the software unless otherwise necessary.

  • Page 186: Output Ports (R00-R03, R10-R13

    CHAPTER 5: PERIPHERAL CIRCUITS (Output Ports) Output Ports (R00–R03, R10–R13) The S1C6S3N2 Series reserves eight bits (4 bits × 2) for general output ports. The output ports R10–R13 can be used as special output ports. Output port memory Table 5.4.1 I/O data memory map (output ports)
  • Page 187 BZ output (output from pin R13). R12 (when FOUT is selected): Special output port data (07CH.D2) Controls the FOUT (clock) output. When "1" is written: Clock output When "0" is written: Low level (DC) output Read-out: Available EPSON S1C6S3N2 TECHNICAL SOFTWARE II-41...

  • Page 188: Example Of Using Output Ports

    R00: Becomes low output Then, the status of the (outputting) pins of output ports R00–R03 is read into B register, and the status of the pins of output ports R10–R13 is read into RAM, DTB. EPSON II-42 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 189 X,7BH Read the value of R00–R03 (being output) to B register B,MX X,7CH Read the value of R10–R13 (being output) to RAM, DTB Y,YDTB MY,MX Addresses for RAM, OUTB and DTB are allocated appropri- ately. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-43...
  • Page 190 R02: No change Set to "0" R01: Becomes low output Fig. 5.4.2 Set to "1" R00: Becomes high output Output result Program X,7BH Make R00 and R03 outputs high MX,1001B MX,1101B Make R01 output low EPSON II-44 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 191 X,7BH Shift high output to left MX,MX NZ,KYSCLP ; Continue until R00–R03 are all low Return to parent routine This routine assumes that the key input evaluation process- ing routine "KYIN" has been prepared separately. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-45...
  • Page 192 Make R10 and R13 high output MX,0001B Returns to parent routine BZOF: X,7CH Make R10 and R13 low output MX,1110B Return to parent routine Note None of these routines affects registers R11–R13 (output pins R11 and R12). EPSON II-46 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 193 4 kHz, then the BZ frequency will still be 4 kHz, even if the second counter advances and becomes odd seconds. As long as "BZ" is not executed again, the frequency will not change to 2 kHz. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-47...

  • Page 194: Programming Note

    In particular, when BZ output is under R10 control, register R13 can be used as a 1-bit general register for read/write. Data in this register has no affect on BZ output (output of pin R13). EPSON II-48 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 195: Lcd Driver

    CHAPTER 5: PERIPHERAL CIRCUITS (LCD Driver) LCD Driver The S1C6S3N2 Series has four common pins and 38 segment pins, so that it can drive an LCD with up to 152 (38 × 4) segments. The driving method is 1/4 duty (1/3 duty or 1/2 duty can be selected with the mask option) dynamic drive.

  • Page 196: Example Of Control Program For Lcd Segment Output

    Pin address assignment table Common 0 Common 1 Common 2 Common 3 SEG(0+4•n) SEG(1+4•n) SEG(2+4•n) SEG(3+4•n) ↑ (2+4•n) (0+4•n) Common 0 Common 1 Common 2 Common 3 Fig. 5.5.2 (3+4•n) (1+4•n) Example of LCD panel EPSON II-50 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 197 " " (single-figure space). When the table is expanded, it corresponds to the character added to the A register in hexadecimal order. Value of A Character Value of A Value of A Fig. 5.5.3 Character Character Diagram of characters EPSON S1C6S3N2 TECHNICAL SOFTWARE II-51...
  • Page 198 LBPX instruction and RETD instruction. Further, expansion from " " (single-figure space) can be done according to the rule below for setting the values of the A and B registers. EPSON II-52 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 199 , Return to parent routine LBPX MX,00010110B Generate "F" (write to segment memory) RETD 00010001B , Return to parent routine LBPX MX,00000000B Generate " " (single-space figure) (write to segment memory) RETD 00000000B , Return to parent routine EPSON S1C6S3N2 TECHNICAL SOFTWARE II-53...
  • Page 200 The pin assignment for the apostrophe and period assign- ments are not shown in (1). They are assigned in the man- ner shown in Figure 5.5.4. Segment data memory assignment table Data Address ↑ Fig. 5.5.4 Example of LCD panel EPSON II-54 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 201 Store the segment data buffer first figure start address to Y register DSSGLP: LDPY A,MY Display: Set the display character LDPY B,MY CALL DSCG Execute "DSCG" XH,0EH Continue up to the eighth figure C,DSSGLP Return to parent routine EPSON S1C6S3N2 TECHNICAL SOFTWARE II-55...
  • Page 202 "DSSP". Program DSSP: MY,0H If low address data is "0" NZ,DSSPRT then make high address data "1" MY,1H DSSPRT: Return to parent routine EPSON II-56 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 203: Lcd Driver Memory Map

    Consequently, data cannot be rewritten by arithmetic operations (such as AND, OR, ADD, SUB). (3) Data output from segment pins selected as DC output will be the data corresponding to the COM0 pins. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-57...

  • Page 204: Clock Timer

    CHAPTER 5: PERIPHERAL CIRCUITS (Clock Timer) Clock Timer The S1C6S3N2 Series has a clock timer built-in. The clock timer can generate timer interrupts at 32 Hz, 8 Hz and 2 Hz. Ordinarily, this clock timer is used for all types of timing functions such as clocks.

  • Page 205: Example Of Using Clock Timer

    (2) Reading the clock timer Specifications This program reads the clock timer data into A register. A register Fig. 5.6.1 Correspondence between clock timer and A register Program X,70H Load the clock timer data into A register A,MX EPSON S1C6S3N2 TECHNICAL SOFTWARE II-59...
  • Page 206 The processing routine for frequencies not set in the clock timer interrupt can be executed by repeatedly calling this subroutine at high frequency. n sec (n+1) sec Time "1" "0" 125 msec Fig. 5.6.2 Timing chart Timeing for executing "TM4" EPSON II-60 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 207 2 Hz and 4 Hz not both "0": Z,BZOF When BESYNF = "0" A,1000B or 4 Hz = "1" NZ,BZOF execute "BZOF", return to parent routine AND MY,XBESYNF XOR 0FH ; In other cases: Reset BESYNF Execute "BZ", return to parent routine EPSON S1C6S3N2 TECHNICAL SOFTWARE II-61...

  • Page 208: Timer Interrupt Memory Map

    Invalid These flags can be reset through being read out by the software. Note Even if these flag interrupts are masked, the flags are set to "1" at the falling edge of the corresponding signal. EPSON II-62 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 209: Clock Timer Timing Chart

    Enable timer 2 Hz interrupt, and mask all others MX,0100B X,7EH Reset clock timer MX,1000B X,79H Reset the timer interrupt factor flags MX,0111B Enable interrupt The generated timer interrupt factor flag is also reset Note through the clock timer being reset. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-63...
  • Page 210 Clock timer 8 Hz Clock timer 2 Hz Program 104H Interrupt vector address of timer interrupt INTI Go to "INTI" if timer interrupt is generated YTIB Buffer address of timer interrupt factor flags EPSON II-64 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 211 (TI) is set to "1" at the falling edge of the corresponding signal. Hence, the presence of an inter- rupt factor is judged by the result of ANDing the factor flag stored in the buffer and the interrupt mask register. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-65...
  • Page 212 MX,XTISF XOR 0FH ; TISF = "1": Reset TISF X,YCKS Increment the second counter data by 1 CALZ CT60 No carry: Return to "INTI" Carry: Execute clock processing for at least a minute "CK", and return to "INTI" EPSON II-66 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 213 Page 0 routine "CTUP" PAGE CTUP: Preparation: Set D flag MX,1H Increment data by 1 with BCD Set tens' place address MX,0H Carry processing to tens' place After process: Reset D flag RTP0: Return to parent routine EPSON S1C6S3N2 TECHNICAL SOFTWARE II-67...

  • Page 214: Programming Notes

    Be very careful when interrupt factor flags are in the same address. (5) Regardless of the setting of the interrupt mask register (ETI), the interrupt factor flag (TI) is set to "1" at the falling edge of the corresponding signal. EPSON II-68 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 215: Input Ports (K00-K03, K10

    CHAPTER 5: PERIPHERAL CIRCUITS (Input Ports) Input Ports (K00–K03, K10) The S1C6S3N2 Series has general-purpose input ports consisting of a total of five bits. Four bits are reserved for pins K00–K03 and one bit is for K10. All five bits of these input ports have interrupt functions.
  • Page 216 1 ms occurs from the time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. EPSON II-70 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 217: Example Of Using Input Ports

    Note When input ports are changed from high to low by pull- down resistor, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-71...
  • Page 218 KYTSOF: X,73H If K00 is low input MX,0001B NZ,KYTSLP CALL BZOF then stop the buzzer KYTSLP: X,77H Loop: K10 pin is low or high? MX,0001B Z,KYTSLP Low input: Loop KYTS High input: Returns to KYTS EPSON II-72 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 219 Disable interrupts X,74H Set the differential registers of K00–K03 LDPX MX,1101B to "1101", Set the interrupt mask registers of MX,0111B K00–K03 to "0111" X,77H Enable interrupt at the rising edge of K10 MX,0100B Enable interrupt EPSON S1C6S3N2 TECHNICAL SOFTWARE II-73...
  • Page 220 Store the value of A register in stack PUSH Store the value of B register in stack PUSH Store the value of the flag group in stack X,7AH (Reset) the input interrupt factor flags Y,YIKB and store in buffer MY,MX EPSON II-74 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 221 If an interrupt has come from more than one pin, this is treated as "multiple key entry", and subroutine "IK0MLT" is executed. Moreover, in case interrupt is inadvertently generated, the error display process "DSER" will be executed. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-75...
  • Page 222 K03 input processing "K03", and return to "INIK" Z,K03 Multiple key entry: Execute multiple key entry processing "IK0MLT", and IK0MLT return to "INIK" This routine assumes that processing routines "K00"–"K03", "IK0MLT" and "DSER" have been prepared separately. EPSON II-76 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 223 No.6 No.5 No.4 No.B No.A No.9 No.8 No.F No.E No.D No.C Disable interrupts X,74H Set the differential registers DFK00–DFK03 LDPX MX,0000B to "0000" MX,1111B Enable K00–K03 interrupt X,7BH Make R00–R03 high output MX,1111B Enable interrupts EPSON S1C6S3N2 TECHNICAL SOFTWARE II-77...
  • Page 224 Continue until four times NZ,K0RDLP A,0H If not high input Z,K0N0ENT execute non-input processing "K0NOENT" and return to "IK0" A,2H If multiple key entry NC,K0MLT execute multiple key entry processing "K0MLT" and return to "IK0" EPSON II-78 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 225 Hence, the K03–K00 interrupt is masked in advance. 2. When input ports are changed from high to low by pull- down resistance, the fall of the waveform is delayed. Hence, when fetching key scan input, set an appropriate wait time. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-79...

  • Page 226: Programming Notes

    = Low status, when the falling edge interrupt is effected and input terminal = High status, when the rising edge interrupt is effected. EPSON II-80 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 227 Be very careful when interrupt factor flags are in the same address. (5) Even when the values of the input data and differential register changes from non-matching to matching, the interrupt factor flag is not set to "1". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-81...

  • Page 228: I/O Ports

    CHAPTER 5: PERIPHERAL CIRCUITS (I/O Ports) I/O Ports The S1C6S3N2 Series reserves eight bits for general-purpose I/O ports. The I/O ports are the allocated into two lots of four bits, P00–P03 and P10–P13, which can be set to either input mode or output mode.

  • Page 229: Example Of Program For I/O Ports

    When the CPU clock is OSC1, this routine sets I/O ports (P00–P03) to input mode, and reads the input data to A register. A register Fig. 5.8.1 Correspondence of I/O ports (input) and A register EPSON S1C6S3N2 TECHNICAL SOFTWARE II-83...
  • Page 230 When the I/O port is set to output mode and a low-imped- Note ance load is connected to the port pins, the value of data written to the register and data read out may differ. EPSON II-84 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 231 (P00–P03), then outputs the value of RAM, YDTB to P10– P13. RAM, YDTB A register P13 register P12 register P11 register P10 register P03 register Fig. 5.8.2 P02 register Correspondence between I/O P01 register ports (output) and A register P00 register and RAM EPSON S1C6S3N2 TECHNICAL SOFTWARE II-85...

  • Page 232: Programming Notes

    Because of this, if a low-imped- ance load is connected and read-out performed, the value of the register and the read-out result may differ. EPSON II-86 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 233: Stopwatch Counter

    CHAPTER 5: PERIPHERAL CIRCUITS (Stopwatch Counter) Stopwatch Counter The S1C6S3N2 Series incorporates a 1/100 sec and 1/10 sec stopwatch counter. The stopwatch counter data can be read out by the software. Further, the stopwatch counter can generate 10 Hz (ap- proximated 10 Hz) and 1 Hz interrupts.

  • Page 234: Example Of Program For Stopwatch Counter

    3. In STOP status, the counter data is maintained until reset or next RUN status occurs. Also, when STOP status changes to RUN status, the data that was maintained can be used for resuming the count. EPSON II-88 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 235 To prevent erroneous reading during carry from the stop- watch counter's low order column (SWL) to the high order column (SWH), the stopwatch counter is stopped during read. The duration of the stop status must be within 976 µs (256 Hz 1/4 cycle). EPSON S1C6S3N2 TECHNICAL SOFTWARE II-89...

  • Page 236: Stopwatch Interrupt Memory Map

    Interrupt has not occurred Writing: Invalid These flags are reset when read out by the software. Note Regardless of the interrupt mask register setting, these flags are set to "1" by overflow of the corresponding counter. EPSON II-90 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 237: Stopwatch Counter Timing Chart

    1 Hz interrupt request stopwatch counter Interrupts are generated by the overflow of their respective counters ("9" changing to "0"). At this time the correspond- ing interrupt factor flags (SWIT0, SWIT1) are set to "1". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-91...

  • Page 238: Example Of Program For Stopwatch Interrupt

    YSWLB Disable interrupts X,7EH Initial start stopwatch counter MX,0010B ; Preparation: Store interrupt factor flag address in the X register SWLP: X,7AH Stop the stopwatch counter Y,7EH MY,1011B ; Store stopwatch interrupt factor flags A,MX EPSON II-92 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 239 No carry up to hours column: Returns to parent routine Carry to higher column: No carry up to hours column, return to parent routine * For details about "CT60", see page 63, "Example of using timer interrupt". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-93...
  • Page 240 Further, the interrupt processing routine is called with CALL instruction and processed. Table 5.9.6 Order of Priority Interrupt Factor Order of priority in program Stopwatch 10 Hz example Stopwatch 1 Hz EPSON II-94 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 241 (SWIT) is set to "1" when the corre- sponding counter overflows. Therefore, the presence of each interrupt factor is judged according to the result of ANDing the factor flag stored in the buffer with the mask register. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-95...

  • Page 242: Programming Notes

    Be very careful when interrupt factor flags are in the same address. (5) Regardless of the setting of the mask register (EISWIT), the interrupt factor flag (SWIT) is set to "1" when the corresponding counter overflows. EPSON II-96 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 243: Event Counter

    CHAPTER 5: PERIPHERAL CIRCUITS (Event Counter) 5.10 Event Counter The S1C6S3N2 Series houses an event counter that counts the clock signals input from outside. The event counter is configured of an eight-bit binary coun- ter (up counter). The counter data can be read out by software.

  • Page 244: Example Of Program For Event Counter

    Controlling procedure for the initial start, stop, start, and Specifications reset of the event counter is sequentially indicated. Program X,0FCH Initial start event counter MX,0101B X,0FCH Stop event counter MX,0000B X,0FCH Start event counter MX,0100B X,0FCH Reset event counter MX,0001B EPSON II-98 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 245: Programming Note

    (EV04–EV07), the counter data is read out mul- tiple times and compared. To prevent erroneous reading of the event counter data, read Programming note out the counter data multiple times for comparison, and use the matching data for the result. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-99...

  • Page 246: Analog Comparator

    CHAPTER 5: PERIPHERAL CIRCUITS (Analog Comparator) 5.11 Analog Comparator The S1C6S3N2 Series incorporates an MOS input analog comparator. This analog comparator, which has two differ- ential input terminals (inverted input terminal AMPM, noninverted input terminal AMPP), can be used for general purposes.

  • Page 247: Example Of Program For Analog Comparator

    AMP circuit ON MX,0001B ; Y,54H Delay: Preparation AMDLLP:ADD Y,0FH Delay loop NZ,AMDLLP ; A,MX Load the result to A register MX,1110B ; AMP circuit OFF Note The delay is made to allow the output to stabilize. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-101...

  • Page 248: Programming Notes

    OFF when it is not needed. (2) After AMPON is set to "1", allow a wait of at least 3 ms for the analog comparator's operation to stabilize before reading out the analog comparator's output data AMPDT. EPSON II-102 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 249: Chapter 6 Initial Reset

    Peripheral Circuits Table 6.1.2 Initial setting values (2) Name Bit Length Setting Value Undefined Segment data Undefined Other peripheral circuits *1 See "3.4 I/O Memory Map". Note Undefined setting values must be initialized by the program. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-103...

  • Page 250: Example Of Initialize Program

    Result of initializing General-purpose register internal circuits Stack pointer Interrupt flag Decimal flag Zero flag Carry flag RAM data (00H–6FH) (80H–9FH) Segment data (C0H–EFH) * The values for the B, X and Y registers are unde- fined. EPSON II-104 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 251 Reset Flag group Note This program is the basic initialize program for the S1C6S3N2 Series. When this program is executed, the internal circuits are initialized as shown in Table 6.2.1. When using the program example, be sure to add any set- ting items necessary for your applications.

  • Page 252: Chapter 7 Summary Of Notes

    (4) Memory is not mounted in unused area within the memory map and in memory area not indicated in this manual. For this reason, normal operation cannot be assured for pro- grams that have been prepared with access to these areas. EPSON II-106 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 253 OSC3 oscillation OFF. (3) To lessen current consumption, keep OSC3 oscillation OFF except when the CPU must be run at high speed. Also, with S1C6S3N2/6S3L2/6S3B2, keep OSCC fixed to "0". EPSON S1C6S3N2 TECHNICAL SOFTWARE II-107...
  • Page 254 After heavy load drive is completed, switch BLS ON and OFF (at least 100 µs is necessary for the ON status) and then return to the normal mode. EPSON II-108 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 255 (3) Resetting the clock timer has no effect on the stopwatch counter, and vice versa. (4) Regardless of the setting of the interrupt mask register (ETI), the interrupt factor flag (TI) is set to "1" at the falling edge of the corresponding signal. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-109...
  • Page 256 = High status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 7.1. EPSON II-110 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 257 Because of this, if a low-imped- ance load is connected and read-out performed, the value of the register and the read-out result may differ. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-111...
  • Page 258 OFF when it is not needed. (2) After AMPON is set to "1", allow a wait of at least 5 ms for the analog comparator's operation to stabilize before reading out the analog comparator's output data AMPDT. EPSON II-112 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 259: Chapter 8 Cpu

    The S1C6S3N2 Series has some 100 types of instructions including arithmetical instructions. All instructions consist of one word (= 12 bits). The following pages contain tables of the instruction set of the 4-bit Core CPU, S1C6200A. "*" mean "not in S1C6S3N2 Series". EPSON S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 260 ← r, YL ↑ ↑ ← ↓ ↓ XH, i XH+i3~i0+C ↑ ↑ ← ↓ ↓ XL, i XL+i3~i0+C ↑ ↑ ← ↓ ↓ YH, i YH+i3~i0+C ↑ ↑ ← ↓ ↓ YL, i YL+i3~i0+C EPSON II-114 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 261 SP-1, M(SP) ← ← SP-1, M(SP) ← ← SP-1, M(SP) ← ← M(SP), SP SP+1 ← ← M(SP), SP SP+1 ← ← M(SP), SP SP+1 ← ← M(SP), SP SP+1 ← ← M(SP), SP SP+1 EPSON S1C6S3N2 TECHNICAL SOFTWARE II-115...
  • Page 262 ↓ ↓ ACPY MY, r M(Y) M(Y)+r+C, Y ↑ ↑ ← ← ↓ ↓ SCPX MX, r M(X) M(X)-r-C, X ↑ ↑ ← ← ↓ ↓ SCPY MY, r M(Y) M(Y)-r-C, Y ↑ ← ↓ EPSON II-116 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 263 A, B, and MX and MY (data memory whose ad- dresses are specified with index registers IX and Registers specified EPSON S1C6S3N2 TECHNICAL SOFTWARE II-117...
  • Page 264 Associated with + ..Add arithmetic and other - ..Subtract ∧ ..... Logical AND operations ∨ ..... Logical OR ∀ .... Exclusive-OR ..Add-subtract instruction for decimal operation when the D flag is set EPSON II-118 S1C6S3N2 TECHNICAL SOFTWARE...

  • Page 265: Appendix

    To terminate assembly (End) MACRO To define macro (Macro) CHECK MACRO DATA LOCAL To make local specification of label LOCAL LOOP (Local) during macro definition LOOP MX,DATA NZ,LOOP ENDM To end macro definition ENDM (End Macro) CHECK EPSON S1C6S3N2 TECHNICAL SOFTWARE II-119...

  • Page 266: Table Of Ice Commands

    Display Evaluation Board CPU internal registers Internal Set Evaluation Board CPU internal registers Registers Reset Evaluation Board CPU #DXY Display X, Y, MX and MY #SXY Set data for X and Y display and MX, MY EPSON II-120 S1C6S3N2 TECHNICAL SOFTWARE...
  • Page 267 Compare contents of ROM with contents of program memory #ROM Set ROM type Terminate Terminate ICE and return to operating system control Command #HELP Display ICE instruction Display Self #CHK Report results of ICE self diagnostic test Diagnosis means press the RETURN key. EPSON S1C6S3N2 TECHNICAL SOFTWARE II-121...
  • Page 268 Central Phone: +852-2585-4600 Fax: +852-2827-4346 101 Virginia Street, Suite 290 Telex: 65542 EPSCO HX Crystal Lake, IL 60014, U.S.A. EPSON TAIWAN TECHNOLOGY & TRADING LTD. Phone: +1-815-455-7630 Fax: +1-815-455-7633 10F, No. 287, Nanking East Road, Sec. 3 Northeast Taipei 301 Edgewater Place, Suite 120...
  • Page 269 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 270 S1C6S3N2 Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue November, 1995 Printed March, 2001 in Japan...

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