Decm Service Assy (7/18) - Pioneer HD-V9000 Service Manual

1
10.5 DECM SERVICE ASSY (5/18)
QQ
3 7 63 1515 0
A
B
TP2004
V+1R2D_Sa
DEMITAS
L 2 0 0 4
A T L 7 0 1 0 - A
C
GNDD
GNDD
TE
L 13942296513
V+1.2_3LADR
TP2001
V+1R2D_Sa
L 2 0 0 3
A T L 7 0 1 0 - A
D GNDD
V+1R8D_Sa
TP2003
DEMITAS
L 2 0 0 2
A T L 7 0 1 0 - A
GNDD
GNDD
E
V+3.3_3LAIO
V+3R3D_1SaSW
TP2002
L 2 0 0 1
A T L 7 0 1 0 - A
www
GNDD
F
A
5/18
72
1
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MeP JTAG
V+3.3_3LAIO
C 2 1 5 3
0 . 0 1 u / 1 6
C N 2 0 0 3
C 2 1 5 2
(RYB)
1 u / 1 0
GND
1 0
TP2320
3_MTDI
MTDI 9
TP2132
NC
8
TP2101
NC
7
TP2102
3_MTRESET
MTRESET
6
TP2133
3_MTMS
MTMS
5
TP2134
V+3.3
4
TP2321
3_MTDO
MTDO
3
TP2135
GNDD 2
TP2322
3_MTCK
MTCK
1
TP2136
N M
GNDD GNDD
V+1.8_3LADR
V+3.3_3LAIO
C 2 0 2 2 C 2 0 5 3
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 2 3 C 2 0 5 4
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 2 4 C 2 0 5 5
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 2 5 C 2 0 5 6
0 . 1 u / 1 0 0 . 1 u / 1 0 TO IC2003
C 2 0 2 6 C 2 0 5 7
0 . 1 u / 1 0 0 . 1 u / 1 0
IC2004
C 2 0 2 7 C 2 0 5 8
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 2 8 C 2 0 5 9
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 2 9 C 2 0 6 0 6:2B;6:3B
0 . 1 u / 1 0 0 . 1 u / 1 0 DDR2_B
C 2 0 3 0 C 2 0 6 1
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 1 C 2 0 6 2
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 2 C 2 0 6 3
3_BMDATA18
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 3 C 2 0 6 4
3_BMDATA22
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 4 C 2 0 6 5
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 5 C 2 0 6 6 3_BMDATA21
0 . 1 u / 1 0 0 . 1 u / 1 0 3_BMDATA20
C 2 0 3 6 C 2 0 6 7
3_BMDATA19
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 7 C 2 0 6 8
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 8 C 2 0 6 9
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 3 9 C 2 0 7 0 3_BMDATA23
3_BMDATA17
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 0 C 2 0 7 1
3_BMDATA16
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 1 C 2 0 7 2
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 2 C 2 0 7 3
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 3 C 2 0 7 4 3_BMDM2
3_BMDQS2
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 4 C 2 0 7 5
3_BMDQS3
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 5 C 2 0 7 6
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 6 C 2 0 7 7
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 4 7 C 2 0 7 8 3_BMDM3
3_BMDATA24
0 . 1 u / 1 0 0 . 1 u / 1 0
C 2 0 7 9
3_BMDATA27
0 . 1 u / 1 0
C 2 0 8 0
V+1.2_3LAVD
0 . 1 u / 1 0
C 2 0 8 1
0 . 1 u / 1 0
3_BMDATA26
C 2 0 8 2
3_BMDATA29
0 . 1 u / 1 0
C 2 0 8 3
3_BMDATA30
0 . 1 u / 1 0
C 2 0 8 4
0 . 1 u / 1 0
GNDD
C 2 0 8 5
0 . 1 u / 1 0
3_BMDATA25
C 2 0 8 6
3_BMDATA28
0 . 1 u / 1 0 GNDD
C 2 0 8 7
3_BMDATA31
0 . 1 u / 1 0
C 2 0 8 8
0 . 1 u / 1 0
3_BMADRS8
3_BMADRS9
3_BMADRS10
GNDD
3_BMADRS12
3_BMADRS6
3_BMADRS7
V+1.2_3LAVD 3_BMADRS11
3_BMADRS3
3_BMADRS2
3_BMADRS4
3_BMADRS5
C 2 0 4 8 3_BMADRS0
0 . 1 u / 1 0
C 2 0 4 9
3_BMBA2
V+1.8_3LADR
0 . 1 u / 1 0 3_BMADRS1
C 2 0 5 0 3_BMBA0
0 . 1 u / 1 0
C 2 0 5 1
0 . 1 u / 1 0
VRef+0R9D_DDR2B
3_BMCS0N
3_BMBA1
GNDD
3_BMCASN
3_BMCKN
DEMITAS 3_BMCKE
GNDD
3_BMCK
C 2 3 3 9
2
1
0 . 1 u / 1 6 3_BMODT
VRef+0R9D_DDR2B
3_BMRASN
2 C 2 3 4 0
1 3_BMWEN
0 . 1 u / 1 6
3_BMDATA0
3_BMDATA6
3_BMDATA7
R 2 2 5 8 C 2 3 4 1
1 0 0 . 1 u / 1 6
R 2 2 5 9 C 2 3 4 2 3_BMDATA2
3_BMDATA3
3_BMDATA4
1 0 0 . 1 u / 1 6
GNDD
GNDD
3_BMDM1
3_BMDATA5
V+1R2D_Sa
3_BMDATA1
L 2 0 0 6
N M
3_BMDM0
V+1.8_3LADR
R 2 0 0 2 0
3_BMDQS1
3_BMDQS0
R 2 0 0 1
0
3_BMDATA14
3_BMDATA9
L 2 0 0 5
3_BMDATA8
N M
GNDD
3_BMDATA15
3_BMDATA12
3_BMDATA11
3_BMDATA13
3_BMDATA10
Note DDR2 DATA/CLK/ADRS/Control signal Line
Same Length, 50 Inpeadance control
IC2001
NLC5015AZB
MPEG DECODER
DEMITAS
x ao
GNDD
y
. i
2
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8
FROM EXT_SYNC
VOCLK,VOCLK_FPGA
VOCLK_FPGA
74.25MHz/74.175MHz/27MHz
C 2 1 4 6
N M
C 2 1 4 7
GNDD
N M
GNDD
GNDD
CLK BUF
VOSKP
GNDD
A29 B29 C29 D29 E29
TP2005
VSS_DDR2_4 VSSO2 VDD33I1 VDD33O1 VSSO8
TP2006
TP2007
TP2008
TP2009
A28 B28 C28 D28 E28
VDDIO_DDR2_3 VSS_DDR2_11 VSSO5 SMODE MTCK
TP2010
TP2011
TP2012 A27 B27 C27 D27 E27
TP2013
VSS_DDR2_3 VDDIO_DDR2_11 VSSO4 VSSO6 PMODE
TP2014
TP2015
A26 B26 C26 E26
D26
BMDQ18 BMDQ22 VSS_DDR2_16 VSSO7
VDDIO_DDR2_23
A25 B25 C25 D25 E25
VDDIO_DDR2_10 VSS_DDR2_29
BMDQ19 BMDQ20 BMDQ21
A24 B24 C24 D24 E24
BMDQ16 BMDQ17 VSS_DDR2_23 VDDIO_DDR2_37
BMDQ23
VDDIO_DDR2_18
A23 B23 C23 D23 E23
BMDQS3 VSS_DDR2_10 BMDM2 VSS_DDR2_35
BMDQS2
VDDIO_DDR2_27
A22 B22 C22 D22 E22
BMDQ27 VDDIO_DDR2_9 BMDQ24 VSS_DDR2_22 BMDM3
VDDIO_DDR2_36
A21 B21 C21 D21 E21
BMDQ30 BMDQ29 VDDIO_DDR2_17 BMDQ26
VSS_DDR2_28
A20 B20 C20 D20 E20
BMDQ31 VSS_DDR2_9 BMDQ28 VDDIO_DDR2_22 BMDQ25
VDDIO_DDR2_35
A19 B19 C19 D19 E19
BMA10 BMA9 VSS_DDR2_15 VSS_DDR2_34
VDDIO_DDR2_26
BMA8
BMA12
A18 B18 C18 D18 E18
BMA7 VDDIO_DDR2_8 VSS_DDR2_21
BMA6
VDDIO_DDR2_34
BMA11
A17 B17 C17 D17 E17
BMA2 VSS_DDR2_27 VSS_DDR2_33
BMA3 VDDIO_DDR2_16
Q Q
BMA5 BMA4
3 6 7 1 3
A16 B16 C16 D16 E16
BMA0 VSS_DDR2_8 VDDIO_DDR2_21 VDDIO_DDR2_33
TP2151
A15 B15 C15 D15 E15
R 2 0 1 0 R 2 0 1 5
BMBA0 BMA1 VSS_DDR2_14 BMBA2 VDDIO_DDR2_25 VSS_DDR2_32
TP2152
RS1/10SR470J-T
RS1/10SR270J-T
A14 B14 C14 D14 E14
BMBA1 VDDIO_DDR2_7 VSS_DDR2_20 VDDIO_DDR2_32
BMCS0N
R0_RDRVB
TP2153
A13 B13 C13 D13 E13
R 2 0 1 1 BMCKN VDDIO_DDR2_15 VSS_DDR2_26
RN1/10SE3000D-T
VSS_CLK2
BMCASN
TP2154
A12 B12 C12 D12 E12
BMCK VSS_CLK1 VDDIO_DDR2_20 VDDIO_DDR2_31
R0_RODTB BMCKE
A11 B11 C11 D11 E11
VDDIO_DDR2_2 VSS_DDR2_13 BMRASN VSS_DDR2_31
BMODT
BMWEN
A10 B10 C10 D10 E10
VDDIO_DDR2_6 VSS_DDR2_19 VDDIO_DDR2_30
BMDQ7 BMDQ6
BMDQ0
A9 B9 C9 D9 E9
B M D Q 4 B M D Q 3 B M D Q 2 V S S _ D D R 2 _ 2 5
V D D I O _ D D R 2 _ 1 4
A8 B8 C8 D8 E8
BMDQ1 VSS_DDR2_7 VDDIO_DDR2_19 VDDIO_DDR2_29
BMDQ5
BMDM1
A7 B7 C7 D7 E7
VDDIO_DDR2_5 VDDIO_DDR2_24
BMDQS0 BMDQS1 BMDM0
VSS_DDR2_30
VSS_DDR2_18
A6 B6 C6 D6 E6
BMDQ8 VDDIO_DDR2_13 VDDIO_DDR2_28
BMDQ9
BMDQ14
A5 B5 C5 D5 E5
VSS_DDR2_6 VSS_DDR2_24
BMDQ11
BMDQ15
BMDQ12
A4 B4 C4 D4 E4
BMDQ10 BMDQ13 VSS_DDR2_17
GPIO1
VDDIO_DDR2_12
A3 B3 C3 D3 E3
VDDIO_DDR2_4 GPIO2
GPIO4
VSS_DDR2_2
VSS_DDR2_12
A2 B2 C2 D2 E2
VDDIO_DDR2_1
GPIO5 GPIO3
GPIO6
VSS_DDR2_5
A1 B1 C1 D1 E1
VSS_DDR2_1 VSSO1 VSSO3 VDD33I2 VDD33O2
GNDD
u163
.
HD-V9000
3
4
2 9 9 4
A 11/18
TP2033
TP2034
R 2 0 4 5 4 . 7 k VIFSYNC
TP2044
R 2 0 4 6 4 . 7 k
VICLK
R 2 0 4 7
R 2 0 5 1
0
F29 G29 H29 J29 K29 L29 M29 N29
VDD33I3 VDD33I4 VOCLK VSSC1 VICLK VSSO18 VIFSCLK VDD33O6
F28 G28 H28 J28 K28 L28 M28 N28
MTDI VUDVD VUD7 VUD1 VUD0 VOC0 VOY4 VOREP
F27 G27 H27 J27 K27 L27 M27 N27
VOSKP VUCKA VUFSYNC VUD2 VOC5 VOC1 VOY5 VOFSYNC
F26 G26 H26 J26 K26 L26 M26 N26
VSSO11 MTDO MTMS VUD3 VOC6 VOC2 VOY6 VOY0
F25 G25 H25 J25 K25 L25 M25 N25
TMOD1 MTRST VUD4 VOC7 VOC3 VOY7 VOY1
VSSO10
F24 G24 H24 J24 K24 L24 M24 N24
VUD5 VOC8 VOC4 VOY8 VOY2
TMOD0
TMOD2
F23 G23 H23 J23 K23 L23 M23 N23
TMOD3 VUD6 VOC9 VIFSYNC VOY9 VOY3
VDDIO_DDR2_44
F22 G22 H22 J22 K22 L22 M22 N22
VSS_DDR2_43 VDD33I6 VDD33I7 VDD33I9 VDD33I13
VSS_DDR2_58 VDD33I11
F21 G21 H21 J21 K21 L21 M21 N21
D1_VREFB VDDIO_DDR2_43 VSS_DDR2_57 VDD_DDR2_7 VSSO15 VSSO17 VSSO20 VSSO22
F20 G20 H20 J20 K20 L20 M20 N20
VSS_DDR2_42 VSS_DDR2_64 VDD_DDR2_13 VDDC2 VDDC11 VDDC15
VSS_DDR2_56
F19 G19 H19 J19 K19 L19 M19 N19
VSS_DDR2_55 VDD_DDR2_6 VSS_DDR2_69 VSSC10 VSSC12 VSSC19
VDDIO_DDR2_42
F18 G18 H18 J18 K18 L18 M18 N18
VSS_DDR2_41 VSS_DDR2_63 VDD_DDR2_12 VSSC9 VDDC10 VDDC14
VSS_DDR2_54
F17 G17 H17 J17 K17 L17 M17 N17
VDDIO_DDR2_41 VSS_DDR2_53 VDD_DDR2_5 VSS_DDR2_68 VSSC8 VDDC9 VSSC18
1 5 0 5 8 2 9
F16 G16 H16 J16 K16 L16 M16 N16
VSS_DDR2_40 VSS_DDR2_52 VSS_DDR2_62 VDD_DDR2_11 VSSC7 VDDC8 VSSC17
F15 G15 H15 J15 K15 L15 M15 N15
VDDA_B1 VSS_DDR2_51 VDD_DDR2_4 VSS_DDR2_67 VSSC6 VDDC7 VSSC16
F14 G14 H14 J14 K14 L14 M14 N14
VDDA_B0 VSS_DDR2_50 VSS_DDR2_61 VDD_DDR2_10 VSSC5 VDDC6 VSSC15
F13 G13 H13 J13 K13 L13 M13 N13
R0_VCALB VSS_DDR2_39 VSS_DDR2_49 VDD_DDR2_3 VSS_DDR2_66 VSSC4 VDDC5 VSSC14
F12 G12 H12 J12 K12 L12 M12 N12
VSS_DDR2_38 VSS_DDR2_48 VSS_DDR2_60 VDD_DDR2_9 VSSC3 VDDC4 VDDC13
F11 G11 H11 J11 K11 L11 M11 N11
VDDIO_DDR2_40 VSS_DDR2_47 VDD_DDR2_2 VSS_DDR2_65 VSSC2 VSSC11 VSSC13
F10 G10 H10 J10 K10 L10 M10 N10
VSS_DDR2_46 VSS_DDR2_59 VDD_DDR2_8 VDDC1 VDDC3 VDDC12
VSS_DDR2_37
F9 G9 H9 J9 K9 L9 M9 N9
V D D I O _ D D R 2 _ 3 9 V S S _ D D R 2 _ 4 5 V D D _ D D R 2 _ 1 V S S O 1 4 V S S O 1 6 V S S O 1 9 V S S O 2 1
D 0 _ V R E F B
F8 G8 H8 J8 K8 L8 M8 N8
VSS_DDR2_44 VDD33I5 VDD33O3 VDD33I8 VDD33I10 VDD33I12
VSS_DDR2_36
ROMD0 ROMA16 ROMA11 ROMA6 ROMA3 ROMA0
F7 G7 H7 J7 K7 L7 M7 N7
VDDIO_DDR2_38
ROMD6
ROMD1 ROMA17 ROMA12 ROMA7 ROMA4 ROMA1
F6 G6 H6 J6 K6 L6 M6 N6
ROMD2 ROMA18 ROMA13 ROMA8 ROMA5 ROMA2
F5 G5 H5 J5 K5 L5 M5 N5
ROMD7
GPIO0
VUSDVD1 VUSDVD2
ROMD3 ROMA19 ROMA14 ROMA9
F4 G4 H4 J4 K4 L4 M4 N4
ROMCSN ROMREN
ROMD4 ROMA20 ROMA15 ROMA10 VUSDATA1 VUSDATA2
F3 G3 H3 J3 K3 L3 M3 N3
ROMBOOT ROMRDY
DAC_SYNC PLL_MD
F2 G2 H2 J2 K2 L2 M2 N2
ROMWEN BASECLK ROMD5 ROMA21 ADATA APPHD
F1 G1 H1 J1 K1 L1 M1 N1
VSSO9 VSSO12 ASCLK VSSO13 ALRCK VDD33O4 APCLK VDD33O5
GNDD
m
Don't use Don't use
co
C 2 1 4 9
N M
CLK(36.666M)
TP2330
GNDD
N M
C 2 1 4 8
N M
GNDD
C 2 1 5 4
GNDD
4:14F
FPGA_I2S
A 4/18
TO FPGA
AUDIO I2S I/F
4
2 8
9 9
A 4/18
FPGA_SARADEC
4:13C
TO FPGA
TO SCALER
SARADEC_SCALER
8:3C
A 8/18
VOFSYNC
#CS_SARA
GNDD
P29 R29 T29 U29 V29
HCLKSEL PCIRESETN VSSC32 VSSO41 VSSO44 VD
P28 R28 T28 U28 V28
VSSO31 WEN SHIRQN ADR11 ADR5 D
P27 R27 T27 U27 V27
VSSO30 WHIRQN EHIRQN ADR12 ADR6 D
P26 R26 T26 U26 V26
VSSO29 SACKN REN ADR13 ADR7 D
P25 R25 T25 U25 V25
VSSO28 EACKN CSN ADR14 ADR8 A
P24 R24 T24 U24 V24
VSSO27 PCIMODE ADR17 ADR15 ADR9 A
P23 R23 T23 U23 V23
VSSO26 WACKN ADR18 ADR16 ADR10 A
P22 R22 T22 U22 V22
VDD33I21 VD
VDD33I17
VDD33I22
VDD33I15
VDD33I19
P21 R21 T21 U21 V21
VSSO25 VSSO34 VSSO37 VSSO40 VSSO43 V
P20 R20 T20 U20 V20
VDDC22 VDDC29 VDDC36 VDDC40 VDDC49 V
P19 R19 T19 U19 V19
VSSC23 VSSC27 VSSC31 VSSC39 VSSC41 V
P18 R18 T18 U18 V18
VDDC21 VDDC28 VDDC35 VDDC39 VDDC48 V
P17 R17 T17 U17 V17
VSSC22 VSSC26 VSSC30 VSSC38 VDDC47 V
9 4 2 8 9 9
P16 R16 T16 U16 V16
VDDC20 VDDC27 VDDC34 VSSC37 VDDC46 V
P15 R15 T15 U15 V15
VDDC19 VDDC26 VDDC33 VSSC36 VDDC45 V
P14 R14 T14 U14 V14
VDDC18 VDDC25 VDDC32 VSSC35 VDDC44 V
P13 R13 T13 U13 V13
VSSC21 VSSC25 VSSC29 VSSC34 VDDC43 V
P12 R12 T12 U12 V12
VDDC17 VDDC24 VDDC31 VDDC38 VDDC42 V
P11 R11 T11 U11 V11
VSSC20 VSSC24 VSSC28 VSSC33 VSSC40 V
P10 R10 T10 U10 V10
VDDC16 VDDC23 VDDC30 VDDC37 VDDC41 V
P9 R9 T9 U9 V9
V S S O 2 4 V S S O 3 3 V S S O 3 6 V S S O 3 9 V S S O 4 2 V
P8 R8 T8 U8 V8
VDD33I14 VDD33I16 VDD33I18 VDD33I20 VDD33O10 VD
P7 R7 T7 U7 V7
AVD3 AVD4 AVD2 RDATA1 RDATA3 R
P6 R6 T6 U6 V6
AVS3 AVS4 AVS2 RDATA0 RDATA2 R
P5 R5 T5 U5 V5
APERR APREQ PLL_MS1 AFSB AFSA U
P4 R4 T4 U4 V4
PLL_MC APDATA PWM1 ADVB ADVA U
P3 R3 T3 U3 V3
VDD33O7 VDD33O8 VDD33O9 ASDB ASDA U
P2 R2 T2 U2 V2
VSSO23 VSSO32 VSSO35 ASCKB ASCKA U
P1 R1 T1 U1 V1
CLK PWM0 APDVD VSSO38 TTCLK V
GNDD
V+3.3_3LAIO
X2001 D S S 1 1 8 1 - A
0 . 1 u / 1 0
OUTPUT GND
3 2
C 2 0 9 6
C 2 0 9 7
VDD STANDBY
1 0 u / 6 . 3 4 1
GNDD
(QYB)
36.666MHz
GNDD
f=36.666MHz TP2064