Kenwood NXR-700 Service Manual page 16

NXR-700
24
DIV
6
4-5. Squelch circuit
The desired noise of the noise component output from IF
system IC_IC12 (pin 18) is extracted by the BPF. After pass-
ing through Q40, it is DC-detected as the squelch voltage by
D17, D18 and input to ADC_IC30 (pin 11).
The MPU mounted in the control unit (X53-413) com-
pares it with a predetermined reference voltage and turns
the Audio signal on and off. The strength of the receiver
signal input from CN5 is output as the RSSI voltage from IF
system IC_IC12 (pin 21), and is input to_IC30 (ADC) pin 12
via IC29 A/2.
+5V
LPF BPF
Q5 CF1
16
CIRCUIT DESCRIPTION
CF2
CF3
D15 D16 D19
SW SW SW
4 6
IC12
1
Analog Wide 5k/4k
2nd local
Analog Narrow
49.5MHz
CF4
2nd local
49.5MHz
4 8 10
IC13
NXDN Narrow
NXDN Very-Narrow
Fig. 19 Demodulator circuits
+5V +5V
LPF
14
IC7
DDS
Q12
Fig. 20 Receiver DDS circuit
CF5
CF7
D20
SW
8 10
21 18
Q40
IC29 (A/2)
5DR
3DR
CF6
14
IC14
4-6. Receiver DDS circuit
The 19.2MHz Internal reference clock produced by trans-
mitter unit (X56-311 A/3) is distributed to CN45 of the re-
ceiver unit (X55-309). It passes through Q39, Q30, and IC8,
and is input to IC7 (DDS-IC) pin 6 as the Master clock. Ap-
proximately 6MHz signal is generated as the 1st-PLL Refer-
ence clock.
IC7 has a resolution of 32 bits for realizing the frequency
step minters than the 1st-PLL comparison frequency. The
generated Reference clock is output via Q12, CF1, and Q5.
CF1 is a Ceramic Filter. It is the BPF for removing unneces-
sary spurious noise included in the generated Reference
clock.
+5V
LPF
6 5
1
IC8
5NR
CN42
15
12
QUAD
IC20
17
(A/2)
D17,18
DET 11 18 22
IC30
12
CN43
+5V
+5V
DIV
LPF
Q39
Q30
CN45