Kenwood NXR-700 Service Manual page 17

4-7. Receiver PLL circuits
The receiver unit (X55-309) has the 1st-PLL circuit for
controlling the VCO that generates the hetero signal to the
first local oscillator, and the 2nd-PLL circuit for controlling
the VCO that generates the hetero signal to the second local
oscillator.
The 1st-PLL circuit consists of the VCO (Q7 and Q8),
the Buffer amplifi er (Q17), the RF amplifi ers (Q16 and Q3),
the PLL-IC (IC5), the Active loop filters (Q2 and Q4) and
the Band switches (Q14, Q10, Q11 and Q59). The signal
in the185.95 through under 194.95MHz band generated by
VCO Q7 and the 194.95 through 203.95MHz band gener-
ated by VCO Q8 is input to IC5 (pin 5) via Q17 and Q16 as
the Fin signal. The 6MHz reference signal generated by the
DDS-IC (IC7) is input to IC5 (pin 8) via Q3. Two signals, Fin
and REFin, are phase-compared as the 100kHz compari-
son frequency by each frequency divider. The VCO output
with the frequency synchronized is input to the 1st-Mixer as
the first local oscillator Upper hetero signal approximately
+8V +8V
LPF
ATT
Q23 Q18
+9LV
Q7
185.95~194.95MHz
+9V Q10
SW
Div.
Q11
Q17
SW SW
Q8
194.95~203.95MHz
+9LV
+5V
LPF
5
1/N
Fin
Q16
IC5
4-8. AVR circuit
The power supply voltage supplied from the power unit
(X45-385 C/5) is distributed from the receiver unit (X55-309)
CN44 to IC24 (8V), IC25 (8V), IC26 (9V), and IC27 (9V) via
the Q52 DC switch. The output of IC24 is supplied to the
1st-IF circuits, the 1st-Local amplifi ers and the IF system IC_
IC12 via IC15 (5V). Further, the output of IC25 is distributed
to IC16 (5V), IC17 (5V), IC18 (5V) and IC19 (5V). The out-
CIRCUIT DESCRIPTION
16 IC30
IC6
ADC
Q14
+9LV
SW
Active
Q59
LPF
Q2,4
+5V
20 +5V
PD
LPF
8
1/R
REFin
Q3
Fig. 21 Receiver PLL circuits
+17dBm via Q17, Q23, and Q18. The control voltage is in-
put to IC30 (ADC) pin 16 via IC6.
Meanwhile, the 2nd-PLL circuit consists of the VCO (Q24),
the Buffer amplifier (Q33), the RF amplifier (Q38, Q22),
and the PLL-IC (IC11). The 99.0MHz signal generated by
Q24 is input to IC11 (pin 5) as the Fin signal via Q38. The
19.2MHz Internal reference clock distributed by the transmit-
ter unit (X56-311) is input as the REFin signal to IC11 (pin 8)
via Q22. Two signals, Fin and REFin, are phase-compared
by each frequency divider as the comparison frequency of
200kHz. The VCO output with the frequency synchronized
is input to IC9 (prescaler IC) pin 2 via Q33 and Q21. The
49.5MHz signal is frequency-divided into halves by IC9 and
is excited by Q53 and distributed. One is input to IC12 (pin
1) via Buffer amplifi er_Q35. The other is input to IC13 (pin
4) via Buffer amplifi er_Q36. Both are input as approximately
–16dBm for the second local oscillator Lower hetero signal.
The control voltage at this point is input to IC30 (ADC) pin
10 via IC33.
+5V +3V +5V
2 7
IC9
ATT
1/2
Q21 Q53
49.5MHz
+9V +9LV
LPF
Div.
Q33 Q24
99.0MHz
+5V
+5V
LPF
5
1/N PD
Fin
Q38
1/R
IC11
put of IC16 is supplied to IF system IC_IC13. The output of
IC17 is supplied to the 2nd-Local amplifi ers. The output of
IC18 is supplied to the 1st-PLL and the 2nd-PLL. The output
of IC19 is supplied to the DDS circuit. The output of IC26 is
supplied to LNA_Q1. The output of IC27 is supplied to the
VCO buffer amplifi ers_Q17, Q33, the 1st-VCO and the 2nd-
VCO via Active ripple fi lters_Q9, Q27, and to the Active loop
fi lter_Q2, Q4 via the Active ripple fi lters_Q6.
NXR-700
+5VA
ATT
Q35
LPF
Div.
+5VD
ATT
Q36
10 IC30
IC33
ADC
20
+5V
LPF
8
REFin
Q22
LPF
LPF
17