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SONY
Explanation
of Instruction
Among
the
8-bit
word-length
instructions,
the following
five
types
of instructions
are capable
of
parallel
execution.
1.
Mu
Iti
p
I
icatio n
1
n
stru ction
s
Depending
on
the multiplicand select
bits
(10,11),
one
of
the
16-bit
data from R1,
ADL,
ADR,
ACC
*
is
selected
as
the multiplicand
(16-bit).
To
this
is
multiplied
the
multiplication coefficient
K.
The
result of multiplication
is
latched
to
P.
The
result
P
is
used by
the next addition
instruction.
This process also
will
correctly
execute
the
problem (-1}x(-1)-*+1.
*
Ace
is
16-bit data,
overflow processing performed.
11
10
MPY
ADRXK
1
AccXK
1
ADLXK
1
1
R1XK
2.
Addition
instructions
Depending on
the
augend
select
bits
(14, 15),
one
of
the
data from
Ace
(22),
R2.
DAL,
or
Null
is
selected
as
the
augend.
The
multiplication resuit of
pre
step.
P
is
added
to
this
augend and
the
result
latched
to
Ace
(22).
15
14
Adder
0+P
1
R2+P
1
Acc+P
1
1
DAL+P
3.
Data
input/output instructions
During
Read
time
(17 is
High), the Input
data
is
latched
to
R1. During Write
time
(17 is
Low),
either
Ace
or
DAR
is
selected
(12,
13)
and
this
data
is
output.
R1 remains
unchanged
during Write.
17
13
12
DRAM
DATA
1
1
X
WRITE
DAR
-*
DRAM
Ace-*
DRAM
Ace
*
DRAM
1
X
X
READ
DRAM
-^
R1
I
4.
Ace
transfer instructions
Depending
on
Ace
transfer
bits
(12, 13),
Ace
can be
transferred
to either
DAL
or
DAR.
1312
Ace
transfer
X
1
1
1
Ace
-*
DAL
Ace
-»
DAR
5.
R1
transfer instructions
Depending on
the
register transfer
bit (16),
R1
data
can be
transferred
to
R2.
If
16
is
High,
R2's value
remains
unchanged.
16
R1
transfer
1
R1-^R2
- 195 -
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