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CARD-PCI/GX Hardware Manual
3.3.2 LIMITED ISA bus
SCE8720C's LIMITED ISA bus is different from standard ISA and its capability is
limited. For details, refer to section 4.10.
For interrupt signals, IRQ5, 9, 10, 11 and 14(IDEINT) for the 280-pin connector, and
IRQ3, 4, 7 and 15 for the 20-pin connector are assigned.
Signal name
(35 pins in total)
SD/SA[15:0]
SA[19:16]
SALATCH
AEN
SBHE#
ROMCS#
MEMR#
MEMW#
28
280-pin connector
I/O
I/O
Address/data bus. Address and data are multiplexed.
Address can be latched by SALATCH signal.
O
Standard ISA signal. The upper 4 bits of the 20-bit
address.
The
SD/SA[15:0].
O
Signal to latch address from SD/SA[15:0].
O
Address enable. Signal which indicates that the current
cycle is DMA or refresh cycle.
O
System byte enable
Signal which indicates that SD[15:8] is enabled.
O
Signal which becomes active at ROM access.
Memory read
O
Signals which request the memory device on the ISA bus
to output data to SD[15:8] or SD[7:0]. This gets active
when the memory address area on the ISA bus, 000000H
to FFFFFFH (all of the 16-MB area) is accessed. This
command applies only if ROMCS#=H when connecting to
the memory device on the ISA bus.
Memory write
O
Signals which request the memory device on the ISA bus
to accept data from SD[15:8] or SD[7:0]. This gets active
when the memory address area on the ISA bus, 000000H
to FFFFFFH (all of the 16-MB area) is accessed. This
command applies only if ROMCS#=H when connecting to
the memory device on the ISA bus.
EPSON
Function description
lower
16
bits
latch
and
generate
Active low
Active low
Active low
Active low
Rev.A
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