Mitsubishi Electric MELSEC-A Series Manual page 163

Network modules
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4
REPLACEMENT OF THE MELSECNET/10 (PLC TO PLC NETWORK)
(3) Q series dedicated link instruction list
The table below shows the dedicated link instructions usable in Q series.
For instruction format of dedicated link instruction and precautions, refer to the following manual.
• Q corresponding MELSECNET/H Network System Reference Manual (PLC to PLC network)
Instruction
Name
SEND
Data sending
Data
RECV
receiving
Other station
READ
word device
SREAD
read
Other station
WRITE
word device
SWRITE
write
Requesting
transient
REQ
transmission
to other
stations
Execution
station
QCPU
SEND:Writes data to the target station (network module)
having the target network number.
RECV:Reads data sent with SEND to the CPU device.
CPU
Network module
Channel 1
Channel 2
Channel 3
SEND
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Reads the CPU device data (in 16-bit units) from the target
station having the target network number.
CPU
Network module
Channel 1
READ
Channel 2
Channel 3
Channel 4
Channel 5
Word device
2594
Channel 6
Channel 7
Channel 8
Writes data (in 16-bit units) to the CPU device of the target
station having the target network number.
(SWRITE can turn on the device of the target station.)
Network module
CPU
Channel 1
Channel 2
Channel 3
WRITE
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Issues "remote RUN" and "clock data read/write" requests to
other stations.
CPU
Network module
Channel 1
Channel 2
Channel 3
REQ
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
: Can be used by both the control and normal stations, × : Cannot be used
Description
Network module
CPU
Logical channel 1 (channel 1)
Logical channel 2 (channel 2)
Logical channel 3 (channel 3)
RECV
Logical channel 4 (channel 4)
Logical channel 5 (channel 5)
Logical channel 6 (channel 6)
Logical channel 7 (channel 7)
Logical channel 8 (channel 8)
Network module
CPU
Word device
2594
Network module
CPU
Word device
361
Network module
CPU
STOP
Target station
QnA/
AnU/
QCPU
QnAS
AnUS(H)
CPU
CPU
×
×
×
×
×
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