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3 Installation and Configuration
3.1 Configuration DIP Switch
SDU13513B00C
SW1-[10:1] Config
CNF[8:0] Config
SW1-[10]
SW1-[9:8]
SW1-[6]
SW1-[7]
SW1-[5:1]
= Required settings when using S5U13U00P00C100 USB Adapter board (SW1-[9:1] = 101000000b)
S5U13513P00C100 Evaluation Board
Rev. 1.2
The S5U13513P00C100 evaluation board incorporates a DIP switch, jumpers, and 0 ohm
resistors which allow it to be used with a variety of different configurations.
The S1D13513 has configuration inputs (CNF[8:0]) which are read on the rising edge of
RESET#. A 10-position DIP switch (SW1) is used to configure the S1D13513 for multiple
Host Bus Interfaces. The following figure shows the location of DIP switch SW1 on the
S5U13513P00C100.
Figure 3-1: Configuration DIP Switch (SW1) Location
All S1D13513 configuration inputs (CNF[8:0]) are fully configurable using DIP switch
SW1 as described below.
Table 3-1: Summary of Power-On/Reset Options
S1D13513
-
Not used
CNF[8:7]
CNF5
Indirect access
See Table 3-2: "CNF[4:0] Setting
CNF6
00000b
CNF[4:0]
Seiko Epson Corporation
Power-On/Reset State
1 (ON)
00b
01b
10b
11b
for CNF[6] = 1b"
Parallel Direct 80 Type 2: 1CS#
(see Table 3-2: "CNF[4:0] Setting for CNF[6] = 1b" )
Installation and Configuration
DIP SWITCH - SW1
0 (OFF)
CLKI3 is the PLL1 clock source
BUSCLK is the PLL1 clock source
OSC1 is the PLL1 clock source
OSC2 is the PLL1 clock source
Direct access
See Table 3-3: "CNF[4:0] Setting for
CNF[6] = 0b"
7
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