Ppc Bus Latency - Motorola MVME2401-1 Installation And Use Manual

Functional Description

PPC Bus Latency

3
Transaction
Beat
Burst Read
Burst Write
Single Read
Single Write
Burst Read
Burst Write
Single Read
Single Write
Burst Read
Burst Write
Single Read
Single Write
Burst Read
Burst Write
Single Read
Single Write
Burst Read
Burst Write
Single Read
Single Write
3-10
The following tables list the latency of PPC originated transactions and the
bandwidth of originated transactions for five different clock ratios: 5:2,
3:2, 3:1, 2:1, and 1:1. The MVME2400 uses a 3:1 clock ratio:
Table 3-5. PPC60x Originated Latency Matrix
32-bit PCI
Beat Beat Beat
1 2 3
40 1 1
5 1 1
22 - -
5 - -
26 1 1
5 1 1
16 - -
5 - -
45 1 1
5 1 1
24 - -
5 - -
33 1 1
5 1 1
19 - -
5 - -
20 1 1
5 1 1
13 - -
5 - -
Total Beat Beat
4 1 2
1 43 29 1
1 8 5 1
- 22 -
- 5 -
1 29 20 1
1 8 5 1
- 16 -
- 5 -
1 48 33 1
1 8 5 1
- 24 -
- 5 -
1 36 25 1
1 8 5 1
- 19 -
- 5 -
1 23 16 1
1 8 5 1
- 13 -
- 5 -
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64-bit PCI
Beat Beat Total
3 4
1 1 32
1 1 8
- - - -
- - - -
1 1 23
1 1 8
- - - -
- - - -
1 1 36
1 1 8
- - - -
- - - -
1 1 28
1 1 8
- - - -
- - - -
1 1 19
1 1 8
- - - -
- - - -
Clock
Ratio
5:2
3:2
3:1
2:1
1:1