Motorola MVME2401-1 Installation And Use Manual page 65

Notes 1. SDRAM speed attributes are programmed for the
tB4
tB3
tB2
tB1(From Idle)
Figure 3-2. Timing Definitions for PPC Bus to SDRAM Access
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following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP =
2 CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK
Periods, tDP = 2 CLK Periods, and the swr_dpl bit is set in
the SDRAM Speed Attributes Register.
2. The Hawk is configured for "no external registers" on the
SDRAM control signals.
3. tB1, tB2, tB3, and tB4 are specified in the following figure.
Block Diagram
tB1(Back-to-Back)
3
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