Hitachi 61HDX98B Manual page 15

BLOCK DIAGRAM EXPLANATION 2H VIDEO
The 2H Video PWB is similar to the Rainfor-
est circuits used in the past. The YUV/YIQ
(480P) and/or the Y-PR/PB (1080I) is routed
through another DM-1 Interface IC for noise
cancellation and level shifting and into the
Rainforest chip, IX01. Here the signal is pre-
pared for the CRT's. Pedestal level detection,
Chroma preparation, OSD RGB from either
the DCU or the Slave Microprocessor is input
here.
Remember that the OSD for Customer usage
such as the Channel numbers, clock, Main
Menu, etc.. is generated by the DM-1 Mod-
ule.
Also, ABL controls the brightness and
Contrast; as well as the color level at this
chip.
The Velocity modulation control signal is
produced from the Rainforest IC. This signal
is a representative of the Peak White compo-
nents of luminance and drives the Velocity
Modulation coils on each CRT.
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