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7901A
A-52.
If
the clock input connection of a latching flip-flop
has an inverting dot, the flip-flop responds to the input sig-
nal while the clock pulse is low.
A-53.
DELAY FLIP-FLOP. The delay flip-flop shown in
figure A-22 is identified by a letter "D" inside the flip-flop
symbol. This type of flip-flop is similar to the latching flip-
flop, except that it responds to the input signal only at the
transition of the clock pulse. The delay flip-flop thus does
not follow changes in the input signal as these changes take
place.
A-54.
GATE FLIP-FLOP. The gate flip-flop is made up
of two logic gates, connected as shown in figure A-23. The
number of inputs to each gate can vary from that shown.
The flip-flop can also be made up of two "nor" gates. The
circuit may have a set output, a clear output, or both.
A-55.
The gate flip-flop functions like an R-S flip-flop,
but it has the advantage that it can "or" inputs without the
addition of a separate "or" gate. Another reason for use of
the gate flip-flop is that if two spare gates are available in
integrated circuits on a circuit card, they can be employed
as an R-S flip-flop without the need to add another inte-
grated circuit to the card.
A-56.
If
the flip-flop is made up of two "nand" gates, as
in figure A-23, it is set by a low input at either A or
B.
Sim-
ilarly, it is cleared by a low input at C or D. When the flip-
flop is in the quiescent state (not undergoing transition),
the inputs at A, B, C, and D are all high.
7900-128
,---
I
A _ _ _ _ _ _
~
B
--------1
c------~
I
D
- - - - - - - - 1
I
L_
-,
I
1
_---1II...----Q
I
1
I
I
I
...._---e----
6
I
I
.-J
Figure A-23. "Nand" Gate Flip-Flop,
Logic Symbol
A-57.
A "nor" gate flip-flop is shown in figure A-24. In
this type of flip-flop all inputs are low when the device is
in the quiescent state. A high input at A sets the flip-flop,
and a high input at B clears it. The outputs cross in the il-
lustration in order to align the set and clear inputs with the
set and clears outputs, respectively.
Logic Symbology
A-58.
In most circuits using the "nand" or "nor" gate
flip-flop, input signals are such that the flip-flop does not
receive high set and clear input signals simultaneously.
If
circuit design does permit this to occur, both the set- and
the clear-side outputs are high for the duration of the con-
dition. The eventual state of the flip-flop is determined by
the input that remains longest in the activating condition.
,-------------,
I
I
1
I
A
~--Q
I
I
'----1--
6
B
I
I
I
L __________
-.J
7900-129A
Figure A-24. "Nor" Gate Flip-Flop Logic Symbol
A-59.
SCHMITT TRIGGER CIRCUIT.
A-60.
The Schmitt trigger circuit shown in figure A-25
can be identified by the letters "ST" appearing in the logic-
diagram symbol. Like the various types of flip-flops this cir-
cuit is a two-state device which does not perform a Boolean
function.
It
serves for level sensing or signal squaring.
It
may
have a set-side output, a clear-side output, or both.
A-61.
When the input voltage at A is below a certain level,
the Schmitt trigger is in the clear state. When the input volt-
age rises above the reference level, the trigger assumes the
set state. Circuit constants establish the reference level.
A
IL-__
S_T_.J-_ _ _
~
7900-130
Figure A-25. Schmitt Trigger Circuit Logic Symbol
A-7
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