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Theory of Operation
A12, and are low during a read or write operation. Since
the flip-flops remain cleared, the control gate to the read-
write logic remains enabled. The Shift-In and Shift-Out
commands are connected through to assembly A9, but are
not used.
4-54.
Data transfer between the controller and disc drive
occurs over a single, transmission-line pair that is shared by
the write data and read data. Two line drivers that are
controlled by the write and read logic, respectively, inter-
face the single transmission pair with assembly A 7 circuits.
The write line driver provides write data interface between
the transmission line and the write formatter circuit, while
the read line driver interfaces the zero-crossing detector
circuit to the line. During a normal write operation, the
Drive Outbus 0 line enables the write gate which, in turn,
enables the write line drive and the write formatter circuit.
Data is passed from the transmission line through the driver
to the write formatter which changes the pulse data to
double-frequency square wave.
As
the write formatter is
toggled by the data, the Write A and Write B lines carry the
double-frequency square wave to the A- and B-gates in
assembly A6 that develop write current for each data- or
clock-bit input. Outputs from the gates are fed to the set of
head-lor head-O write coils that are enabled. Selection of
the enabled set of coils is made by energizing one of the
two head drives as discussed in paragraph 4-43.
4-55.
When the write gate in assembly A 7 is enabled, a
Write Gate signal is passed from assembly A 7 to the write
enable circuit in assembly A6. The write enable circuit
inhibits the read enable gate and turns on the write-current
sink to complete the A-gate and B-gate circuits to allow
flow of write current through the selected head coil. Cur-
rent flowing in the circuit is further controlled by a De-
crease Write Current input from assembly A 7 to assembly
A6. This control is a product of a >Track-128 output from
the destination address register in assembly All. The out-
put is high only when a cylinder address received from the
controller is greater than 127. In assembly A6, the high
>Track-128 output reduces the write current source by
approximately 20 percent on disc cylinders 128 through
202 to optimize write characteristics over the entire disc.
4-56.
An erase function produces two gaps on either side
of the recorded data and occurs during the write operation.
This provides a band between the data tracks, and prevents
the head from reading the data on adjacent tracks during a
read operation. An erase operation is initiated by making
Drive Outbus 2 into assembly A 7 go high when a write
operation also has been selected. A low Erase Gate signal is
passed from assembly A 7 to assembly A6 and turns on an
erase current gate sense circuit to apply a dc current
through the erase coil of the selected head to provide an
erase band on either side of the disc data track.
4-57.
A read operation is enabled when Drive Outbus 1
becomes high in assembly A 7. The enabled read gate turns
on the read line driver and connects the zero-crossing de-
tector to the transmission line pair. In assembly A6, the
write enable circuit is disabled which permits the read
enable gate and subsequent processing circuits to operate
4-8
7901A
normally. As the heads fly over the selected cylinder, the
data is retrieved from the disc surface in analog form and is
gated through the read enable gate to a preamplifier. The
output of the preamplifier is a signal of varying amplitude
and frequency, with each signal peak representing a clock
or data bit. The output is passed through a low-pass filter
and a differentiator, whose output is an analog signal with
each clock or data bit now represented by the zero-crossing
point. Line-isolation drivers pass this Read A and B infor-
mation from assembly A6 to the zero-crossing detector
circuit in assembly A 7 where an analog-to-double-frequency
square wave conversion occurs. The information is then
passed through a pulse generator where the information is
transformed into serial data. The read data is then con-
nected to the transmission line through the enabled read
driver.
4-58.
A read/write error detection circuit in assembly
A 7 monitors operation of various read/write functions in
assemblies A6 and A 7. The assembly A 7 circuits that are
monitored include the write, erase, and read gates. An ac
write current detect circuit in assembly A 7 provides a
monitor indication of A- and B-gate operation in assembly
A6, while the dc write current detect circuit in assembly A 7
provides monitor indications for the write current sink in
assembly A6. An erase detect line between the error detec-
tion circuit in assembly A 7 and the erase current gate sense
circuit in assembly A,6 also provides monitor indications.
The Multi-Head Detect line from assembly A6 to assembly
A 7 provides an error signal when both head drives are
gated-on simultaneously. When an error occurs in any of
the circuits, an associated cross-coupled gate in the read/
write error detection circuit is toggled. Table 4-1 lists
typical error conditions and indications at test points TP4,
TP5, and TP6.
Table 4-1. Read/Write Fault Conditions
ILLEGAL
A7TP4
A7TP5
A7TP6
CONDITION
Straddle
erase
current
flowing
1
0
0
without an erase gate.
A write gate without straddle erase
0
1
0
current.
Simultaneous read gate and erase
1
1
0
gate.
More than one head selected at
1
0
1
once.
A write gate without ac write cur-
l
0
1
rent (data).
DC write current without a write
0
1
1
gate.
An erase gate without an Access
1
1
1
Ready signal.
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