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790lA
select information is gated through to write drive/read
preamplifier assembly A6 where the head-l drive is enabled.
When a low Drive Outbus 1 condition exists in assembly
All, the Head
1
output from the Head Address flip-flop is
low and the head-O drive is enabled in assembly A6.
4-44.
The Control Outbus 3 through 7 lines from the
controller assembly Al2 carry the sector select logic, and
are passed to assembly All on the Drive Outbus 3 through
7 lines. The sector address is compared with the output of
the sector counter in a five-bit sector compare register.
Four bits of the input address are applied directly to the
head-and-sector address register by the Drive Outbus 4
through 7 lines. The most significant bit of the sector
address, which is carried on Drive Outbus 3, is applied
directly to the sector compare register through a separate
flip-flop. Both the head-and-sector address register and the
flip-flop connected in the Drive Outbus 3 line are clocked
by the low Drive Set Head and Sector signal when the
head-and-sector address is legal.
4-45.
The sector counter in assembly All is set by the
Sector Transducer pulse input from sector transducer as-
sembly A2. A slotted skirt that is divided into 24 equal
segments is mounted on the disc hub and rotates as the disc
is turned by the spindle motor. A light source located on
one side of the skirt and a photocell on the other provides
electrical impulses as the skirt rotates. An index slot is
located approximately one-quarter of a sector past the
zero-sector slot and is used as a reference point for counting
the sectors. Each revolution of the disc produces 24 sector
pulses and an index pulse which are applied to assembly
All on the Sector Transducer line.
4-46.
Sector pulses are first applied to an adjustable
time delay circuit to permit synchronization of the
pulses with disc data. The pulses are then processed by
two one-shot stages that provide sector pulse inputs to
the speed-up sense circuit and speed-down sense circuit,
and separate the sector pulses and index pulse. When
sector pulse count rate in the speed-up sense circuit
indicates that disc speed is above 80 percent nominal,
the circuit develops a low Speed Up signal that is
described in paragraph 4-24. The speed-down sense
circuit develops a low Speed Down signal when the disc
speed is below 0.2 percent of nominal as indicated by
the sector pulse count rate.
4-47.
Each index pulse clears the sector counter and
Sector Pulse Input flip-flop. This action is followed by
application of the sector pulses to the divide-by-24
counter. Output from the sector counter is fed to the
sector compare register where a comparison between the
sector address and the sector pulse count is made. When
the two inputs are equal, a high Sector Compare output
is passed through the fixed-status circuit in assembly
Al2 and sent to the controller as
a
low Select and
Sector
Compare
indication.
Sector pulses are
also
applied to a 24-microsecond one-shot that provides a
Sector Pulse output to
the
fixed-status
circuit in
assembly A12. With select circuits enabled, a low Select
and Sector Pulse indication is passed to the controller.
Theory of Operation
4-48.
In the event that the Set Cylinder and Set Head
and Sector signals are low at the same time in assembly
A12, the R see Home line becomes low. In assembly AlO,
the conditi n causes the Home Latch to be set, and pro-
vides a low Servo Inhibit and high Seek Home condition as
described i paragraph 4-26. After the carriage is returned
to the h05e position, the controller must issue new cyl-
inder and h
l
ad-and-sector addresses.
4-49.
InJlassemblY All, if an illegal cylinder address or
an illegal h ad-and-sector address are detected by the illegal
address decode and illegal sector decode circuits, a low
Illegal Address output is sent to assembly AlO. The signal
sets a Seek Check flip-flop which provides an output to
assembiy Al2. The controller obtains the Seek Check indi-
cation on the Control Inbus
1
line when the Control Out-
bus 7 line is low.
4-50.
READ/WRITE CONTROL.
4-51.
Read, write, and erase control of the disc drive is
exercised when the controller makes the Control line go
low and places the Read, Write, or Erase command on the
.Qontrol Outbus 0 through
2
lines. The low Control Outhus
1
signal is used to request a read operation, while the low
Control Outbus
0
and
2
signals request a write-erase opera-
tion. These inputs are passed through I/O multiplex as-
sembly Al2 and connected to read/write control assembly
A 7 via the Drive Outbus 0 through 2 lines. Connections also
are made between the Control Outbus
3
and
4
circuits in
assembly Al2 and the Drive Outbus 3 and 4 lines to
assembly A 7. These latter two inputs control a pair of
flip-flops in assembly A 7 that provide Shift-In or Shift-Out
signals that are not used in the disc drive.
4-52.
When Control and Control Outbus 0 and 2 are low
in assembly Al2, the Drive Outbus 0 and 2 signals are sent
from assembly Al2 to assembly A 7 . Simultaneously, a
Select-and-Control signal, which is the product of the low
Control input to assembly Al2, is passed to assembly A 7.
When the controller makes the Control Outbus 7 line in
assembly Al2 go low during the period that the Control
line is low, a low Select-and-Control-and-Outbus 7 indica-
tion is sent to assembly AlO to clear the Attention flip-flop
and remove the first-status indication to assembly A12.
4-53.
The input circuits of the write, erase, and read
logic of read/write control assembly A 7 contain provisions
to inhibit operation under certain conditions. An output
from the read/write error detection circuit provides an
Unsafe signal to the logic and inhibits a read or write
operation when an error is detected in any circuit being
monitored. The same error indication inhibits operation of
the head select logic. When a data protect function is
selected by setting DATA PROTECT switch S9 to the ON
position, a write-erase function is inhibited, but a read
operation can be performed. The output of two flip-flops
that are connected in the shift·in, shift-out circuits in as-
sembly A 7 also are connected to the input of the read,
write, and erase logic. These flip-flops are controlled by the
Drive Outbus 3 and 4 inputs to assembly A 7 from assembly
4-7
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