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7901A
the home latch circuit is set for normal operation and
removes the Servo Inhibit and Seek Home output to as-
sembly A9. The high Heads Loaded signal in assembly A10
is applied to a seek timer circuit that is described later in
this section, and to a gate that controls the Drive Ready
indication.
4-28.
With the Heads Loaded and Load Switch signals
high in assembly A10, and after time-out of the drive ready
delay circuit, the Drive Ready signal becomes high and is
passed to I/O multiplex assembly A12. A low Drive Ready
signal also sets a flip-flop in the first-status circuit to pro-
vide a high First-Status signal to assembly A12. A high
Drive Ready signal also is applied to the output gate in the
position delay circuit. While the carriage and heads are in
the home position, a low Position Match signal is applied to
the position delay circuit in assembly A10. Outputs from
the position delay circuit inhibit the seek timer, provide a
high Access Ready signal to assembly A12, and set the
Attention flip-flop which provides a high Attention output
to assembly A12. During the foregoing events, a low Drive
Ready Lamp signal also is passed from assembly A10 to
indicator assembly A1 to light the DRIVE READY lamp.
4-29.
I/O multiplex assembly A12 interfaces the disc
drive with the controller. With a match between the Select
A and B logic from assembly A1 and the Select
1
and 2
logic from the controller, and with Select Enable high, the
assembly logic is enabled. The high Drive Ready and Access
Ready indications from assembly A10 are gated through to
the controller as low Select and Drive Ready, and low
Select and Access Ready indications. With Attention high
in assembly A12, the controller can pulse the Control
Outbus 6 line low to identify the disc drive unit number.
This identification is made by making one of the Control
Inbus 0 through 4 signals from assembly A12 to the con-
troller go low. The low line is established by the Select A
and B logic applied to the address decode circuit as dis-
cussed in paragraph 4-19. The controller also can determine
first-status, seek check, data protect, software protect, or
drive fault conditions over the Control Inbus 0 through
4
lines. These status indications are gated through assembly
A12 when the controller makes the Control Outbus 7 line
go low. Development of, a first-status indication, as dis-
cussed in paragraph 4-28, and the seek check, data protect
and drive fault functions are described in following para-
graphs. The Software Protect signal in assembly A12 is
developed by setting the SOFTWARE PROTECT switch on
the disc drive chassis. The function is used to inhibit a write
operation in the address field of a disc sector.
4-30.
CARRIAGE POSITION CONTROL.
4-31.
Carriage movement and position is controlled by
encoder assembly A9 logic, which receives channel A, Band
C information from the head encoder assembly, and by a
Velocity Command received from sector cylinder assembly
All. Channel C information through assembly A9 is used
to position the carriage and heads in the home position as
discussed in paragraph 4-26. Further control of the carriage
is achieved by the controller through I/O multiplex
Theory of Operation
assembly A1 . A low Set Cylinder signal from the con-
troller to a embly A12 starts the carriage positioning
process. This signal indicates that a cylinder address is
present on t e Control Outbus 0 through 7 lines and, in
conjunction
ith the Access Ready signal from assembly
A10, provide a Seek command to assembly All. The low
Set Cylinder signal in assembly A12 also develops a high
Drive Set Cyl nder signal that is passed to assembly A10 to
clear the Atte tion flip-flop.
4-32.
The cylinder address on the Control Outbus 0
through 7 lin s is passed through isolation amplifiers in I/O
multiplex ass mbly A12, and sent to sector cylinder as-
sembly All n the Drive Outbus 0 through 7 lines. All lines
are passed th ough an illegal-address decode circuit.
If
the
cylinder addr ss is legal « cylinder 202), an enabling signal
is applied, wi h a Seek command from assembly A12, to a
gate that str bes the incoming cylinder address into the
destination a dress register. The Seek command also makes
the Cylinder
atch output to assembly A9 go high which,
in turn, mak s the Position Match output to assembly A10
go high. In
sembly A10, the high Position Match signal
makes the A cess Ready signal to I/O multiplex assembly
A12 go low and, in conjunction with the high Heads
Loaded signal, starts the seek timer.
4-33.
Tim -out of the seek timer circuit in assembly A10
is approxima ely 850 milliseconds.
If
the carriage has not
moved to the new cylinder address within that time period,
the seek tim r sets the Drive Fault flip-flop. A high Drive
Fault signal is sent to I/O multiplex assembly A12 to
develop a
10
output that is sent over the Control Inbus
4
line to the c ntroller. In assembly A10, a low Drive Fault
indication in ibits a gate in the servo relay circuit, which
causes servo relay K1 in servo amplifier/regulator A4 to
de-energize.
his condition connects a Retract signal from
assembly A4 through a carriage retract switch back to
assembly A4 s a high Retract Switch Closed'signal. A fixed
voltage is ap lied to the linear motor through relay K1
causing the arriage to return to the retracted position.
Concurrently the Drive Ready indication from assembly
A10 to asse bly A12 goes low, the Drive Ready Lamp
signal from
sembly A10 to indicator assembly A1 goes
high, and a ow Drive Fault Lamp indication is sent to
assembly Al. In assembly A1, the DRIVE FAULT lamp is
lighted and t e DRIVE READY lamp is extinguished. The
disc drive is ow in the original state and, with the LOAD
switch still
0
,starts a cycle toward the home position and
requires new controller commands as described under Drive
Enable and
otor Control, paragraph 4-17.
4-34.
Duri g normal operation, with the seek timer cir-
cuit in asse bly A10 continuing a time-out cycle, the
cylinder add ess stored in the assembly All destination
address regis er and the carriage address in the current
address regis er are compared in the address difference
adder circuit.
If
a seek is forward (away from cylinder 000),
the Carry
0
tput is low. When a seek is conducted in the
reverse direct on, Carry is high. During a seek operation, the
Cylinder Mat h output from assembly All also is high. The
two conditio s are applied to assembly A9 to determine the
operation of he current command gates. A low Carry signal
4-5
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