Data Writes (Divider Reset); Fout Output And 1 Hz Carries - Epson Q41454351000200 Applications Manual

RTC - 4543 SA/SB

7-3. Data writes (Divider Reset)

CE
WR
CLK
DATA
Timer,counter
Divider reset
Pulse
Carry stop
Pulse
After the counter is reset, carries to the seconds digit are halted.After the data write operation,
the prohibition on carries to the seconds counter is lifted by setting the CE pin low.
Complete data write operations within tCE (Max.) = 0.9 seconds, as described earlier.

7-4. FOUT output and 1 Hz carries

CE
WR
CLK
1Hz
FOUT
During a data write operation, because a reset is applied to the Devider counter (from the 128 Hz
level to the 1 Hz level) after the CE pin goes high during the time between the falling edge of the first
clock cycle and the rising edge of the second clock cycle, the length of the first 1 Hz cycle after the
data write operation is 1.0 s
intervals.
The 1-Hz signal that is output on FOUT is the internal 1-Hz signal with a 15.6-ms shift applied.
1 2
N Seconds
s1 s2 s4 s8 s10
N seconds
t
CES
t
CLK
+0 / −7.8ms
s20 s40 y8 y10 y20 y40
0 seconds
0
1.0 s
-7.8 ms
15.6 ms
t t
+ + Subsequent cycles are output at 1.0-second
CES CLK.
Page - 8
52
y80
N seconds
15.6 ms
MQ252-04