Fujitsu MB91401 Datasheet page 26

MB91401
CPU
• The instruction fetch is not done from D-bus, and does not set the code area on D-bus RAM.
• Set neither stack area nor the vector table on the instruction RAM.
• The following operations may be performed when the instruction immediately followed by a DIVOU/DIVOS
instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event
or emulator menu:
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(3) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (1) .
• The following operations are performed when the ORCCR/STILM/MOVRi and PS instructions are executed.
(1) The PS register is updated in advance.
(2) Executing of EIT processing routine (user interrupt NMI)
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1) .
• Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt
handler to break or the PS flag to update its display setting when the debugger is being used. As the micro-
controller is designed to carry out reprocessing correctly upon returning from such an EIT event in either case,
it performs operations before and after the EIT as specified.
1. When (a) user interrupt and NMI are accepted or (b) step is executed or (c) break is done by the data
event or the menu of the emulator in the instruction immediately before the instruction of DIV0U/DIV0S,
the following operation might be done.
(1) The D0 and D1 flags are updated in advance.
(2) An EIT handling routine (user interrupt, NMI, or emulator) is executed.
(1) Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are
updated to the same values as in (3) .
2. When ORCCR, STILM, MOV Ri, and PS each instruction is executed to permit interrupt with the user
interrupt and the NMI factor generated, the following operation is done.
(1) The PS register is updated in advance.
(2) The EIT processing routine (user interrupt, NMI or emulator) is executed.
(3) Upon returning from the EIT, the above instructions are executed and the PS register is updated to
the same value as in (1).
• Do not access the data to the cache memory at the control register of the instruction cash and RAM mode
immediately before the instruction of RETI.
• If one of the instructions listed below is executed, the SSP or USP* value is not used as the R15 value and,
as a result, an incorrect value is written to memory.
• Only ten following kinds of instructions that specify R15 as Ri correspond.
AND R15, @Rj
OR R15, @Rj
EOR R15, @Rj
XCHB @Rj, R15
* : As for R15, there are no realities. When R15 is accessed from the program, SSP or USP is accessed by the
state of "S" flag of the PS register. Please specify general registers other than R15 when ten above-mentioned
instructions are described by the assembler.
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ANDH R15, @Rj ANDB
ORH R15, @Rj ORB
EORH R15, @Rj EORB
R15, @Rj
R15, @Rj
R15, @Rj
Prelminary
2004.11.12