Fujitsu MB91401 Datasheet page 38

MB91401
(Continued)
Address
0000_067C
H
CSER [R/W]
0000_0680
H
00000001
0000_0684
H
00XXXXXX
0000_0688
H
to
0000_0FFC
H
*1 : An initial value is a different register at the reset level. The display is the one at the INIT level.
*2 : An initial value is a different register at the reset level. The display is due to the INIT level by INITX.
*3 : An initial value is set by the WTH bit of the mode vector.
Address
0000_1000
H
0000_1004
H
0000_1008
H
0000_100C
H
0000_1010
H
0000_1014
H
0000_1018
H
0000_101C
H
0000_1020
H
0000_1024
H
0000_1028
H
to
0000_FFFC
H
38
Register
0 1
CHER [R/W]
XXXXXXX1
RCR
00XXXXXX
Register
0 1
DMASA0
XXXXXXXX XXXXXXXX
DMADA0
XXXXXXXX XXXXXXXX
DMASA1
XXXXXXXX XXXXXXXX
DMADA1
XXXXXXXX XXXXXXXX
DMASA2
XXXXXXXX XXXXXXXX
DMADA2
XXXXXXXX XXXXXXXX
DMASA3
XXXXXXXX XXXXXXXX
DMADA3
XXXXXXXX XXXXXXXX
DMASA4
XXXXXXXX XXXXXXXX
DMADA4
XXXXXXXX XXXXXXXX
2
TCR [R/W]
00000000*
2
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
[R/W]
XXXXXXXX XXXXXXXX
Prelminary
2004.11.12
Block
3
1 Memory IF
Reserved
Block
3
DMAC
Reserved