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b)
Within 400 ns of receiving a command when the DRQ bit is not set
c)
Between data transfer blocks of the PIO data-in/PIO data-out command when the
DRQ bit is not set
d)
After data block transfer with the PIO data-out command when the DRQ bit is not
set
e)
During DMA transfer when the DRQ bit is not set
In all other cases, the ODD does not set BSY.
If BSY is set after RESET- is negated, the SRST bit is set, or a Device Reset command is
issued, it remains set until the ODD completes the internal reset process.
!
DRDY (Device Ready) is always 1, except at the time after reset is made until the next
command is issued.
!
For SERVICE, set the same value as that of DRDY. The SERVICE bit should be ignored
from the standpoint of compatibility.
!
DRQ (Data Request) indicates that the ODD can transfer one byte or one word to or from the
host. When DRQ is 1, the ATAPI Interrupt Reason register of the current packet command is
effective.
!
CORR (Corrected Data) is always 0.
!
CHECK indicates that an error occurred in command processing. The Error register contains
additional information on the cause of the error. When the ODD sets CHECK to 1, the items
below are not changed until a new command is received or the ODD is reset.
!
CHECK bit of the Status register
!
Error register
!
Device/Head register
C156-E142-02EN
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