Fujitsu C145-C037-01EN Product Description page 51

Connector Return
pin line pin Compati mode
number number
2 20 Data 1
3 21 Data 2
4 22 Data 3
5 23 Data 4
6 24 Data 5
7 25 Data 6
8 26 Data 7
9 27 Data 8
10 28 Acknowledge
(ACK)
11 29 Busy
12 28 Paper Empty (PE)
13 28 Select (SLCT)
14 30 Auto Feed XT
Table 5.1 Parallel interface signals (continued)
Signal
Direction
Nibble mode
Input
Input
Input
Input
Input
Input
Input
Input
Output
Printer Clock
Output
Printer Busy
Output
Ack Data Req
Output
X Flag
Input
Host Busy
Description
• Data 1 to Data 8 signals correspond to parallel
data bits 1 to 8.
• Data 8 is the most significant bit.
• All signals must go high at least 0.5 s before
the falling edge of the Data Strobe signal, and
must stay high for at least 0.5 s after the rising
edge.
• Pulse signal indicating data reception completed
(or data reception enabled) status
• Issued when the printer switches from offline to
online
Reverse data transfer phase:
This signal goes high when data being sent to the
host is established.
Reverse idle phase:
This signal is set low then goes high to interrupt the
host, indicating that data is available.
Data cannot be received when this signal is high,
e.g., if the buffer is full or an error occurs.
Reverse data transfer phase:
Data bit 3, data bit 7, then forward path (host to
printer) busy status
This signal goes high if paper runs out.
Reverse data transfer phase:
Data bit 2, then data bit 6
Reverse idle phase:
This signal is set high until the host requests data
and, after that, follows the Data Available signal.
This signal goes high when the printer is selected
(online), and goes low when the printer is deselected
(offline).
Reverse data transfer phase:
Data bit 1, then data bit 5
Reserved (*1)
Reverse data transfer phase:
This signal is set low when the host can receive data,
and goes high when the host has received data.
Following a reverse data transfer, the interface enters
the reverse idle phase when the Host Busy signal goes
low and the printer has no data.
Reverse idle phase:
This signal goes high when the Printer Clock signal
goes low so that the interface re-enters the reverse
data transfer phase. If it goes high with the 1284
Active signal low, the 1284 idle phase is aborted and
the interface returns to the compatibility mode.
5-3