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Connector
Return
pin
line pin
Compati mode
number
number
4
22
Fault
5
23
Paper Empty (PE)
6
24
Data 1
7
25
Data 2
8
26
Data 3
9
27
Data 4
10
28
Data 5
11
29
Data 6
12
30
Data 7
13
31
Data 8
14
32
Input Prime
(IN PRM)
15
33
Data Strobe
(DSTB)
16
34
(Select In)
Table 5.2 Parallel interface signals (continued)
Signal
Direction
Nibble mode
Output
Data Available
Output
Ack Data Req
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Host Clock
Input
1284 Active
Description
This signal goes low under the following printer
conditions:
(1) Offline
(2) Paper out
(3) Cover open
(4) Other printer error
Reverse data transfer phase:
This signal is set low when the printer is ready to
send data to the host. During the data transfer, it is
used as data bit 0 (LSB), then data bit 4.
Reverse idle phase:
This signal is used to indicate that data is available.
This signal goes high if paper runs out.
Reverse data transfer phase:
Data bit 2, then data bit 6
Reverse idle phase:
This signal is set high until the host requests data
and, after that, follows the Data Available signal.
• Data 1 to Data 8 signals correspond to parallel
data bits 1 to 8.
• Data 8 is the most significant bit.
• All signals must go high at least 0.5 s before
the falling edge of the Data Strobe signal, and
must stay high for at least 0.5 s after the rising
edge.
Reserved (*1)
• Strobe pulse for reading data (Data 1 to Data 8).
The printer reads data when this signal is low.
• The pulse width must be 0.5 s or more at the
printer's receiving terminal.
This signal is set high when the host requests the
reverse data transfer phase (nibble mode).
Reserved (*1)
This signal goes high to cause the printer to enter the
reverse data transfer phase (nibble mode).
5-9
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