Motorola DSP56600 Manual page 3

iv Optimizing DSP56300/DSP56600 Applications
SECTION 4
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . .4-1
4.2 CONSERVING CORE MIPS BY WORKING IN
PARALLEL. . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
4.3 USING SLOW, LOW-COST MEMORIES . . . .4-4
4.4 SERVICING A PERIPHERAL . . . . . . . . . . . . .4-6
4.5 DATA TRANSFER OPTIMIZATION HINTS. .4-12
SECTION 5
5.1 THE INSTRUCTION CACHE. . . . . . . . . . . . . .5-1
5.1.1 Cache Sectors. . . . . . . . . . . . . . . . . . . . . . .5-3
5.1.2 Control of Sector Allocation. . . . . . . . . . . . .5-4
5.1.3 Cache Burst Mode. . . . . . . . . . . . . . . . . . . .5-6
5.2 MEMORY SWITCH . . . . . . . . . . . . . . . . . . . . .5-9
5.3 USING THE BOOTSTRAP ROM. . . . . . . . . .5-11
SECTION 6
6.1 DATA ALU PIPELINE INTERLOCKS . . . . . . .6-1
6.1.1 What are the Data ALU Pipeline
Interlocks? . . . . . . . . . . . . . . . . . . . . . . . . . .6-2
6.1.2 Avoiding Data ALU Pipeline Interlocks . . . .6-3
6.1.2.1 Code Reorder . . . . . . . . . . . . . . . . . . . . .6-3
6.1.2.2 Loop Unrolling. . . . . . . . . . . . . . . . . . . . .6-4
6.1.2.2.1
6.1.2.2.2
6.1.2.3 Saving Interlocks by Using the TFR
Instruction. . . . . . . . . . . . . . . . . . . . . . . .6-6
6.2 ADDRESS GENERATION PIPELINE
INTERLOCKS . . . . . . . . . . . . . . . . . . . . . . . . .6-7
6.2.1 What are the Address Generation Pipeline
Interlocks . . . . . . . . . . . . . . . . . . . . . . . . . . .6-7
6.2.2 Avoiding Address Generation Pipeline
Interlocks . . . . . . . . . . . . . . . . . . . . . . . . . . .6-8
USING THE DMA . . . . . . . . . . . . . . .4-1
INSTRUCTION CACHE AND
MEMORY FEATURES . . . . . . . . . . .5-1
PIPELINE INTERLOCKS . . . . . . . . .6-1
Loop Unrolling in N Array Scale
Routine. . . . . . . . . . . . . . . . . . . . . . . .6-4
Unrolling in Memory Array Copy
Routine. . . . . . . . . . . . . . . . . . . . . . . .6-5
MOTOROLA