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6.4.1.3
JMP to Last Addresses of a Do-Loop (LA or LA–1)
Whenever I1 is any type of JMP with the target address equals to
(LA) or to (LA–1) then the instruction following the instruction at
(LA) will be delayed by 2 or 1 clock cycles, respectively.
6.4.1.4
RTI to Last Addresses of a Do-Loop (LA or LA–1)
Whenever I1 is an RTI instruction with the return address being
either (LA) or (LA–1), then the instruction at (LA) will be delayed by
2 or 1 clock cycles, respectively.
6.4.1.5
MOVE from the System Stack High (SSH)
Whenever I1 is a MOVE from SSH and it is located at (LA–2) then
the instruction following the instruction at (LA) will be delayed by 1
clock cycle.
6.4.1.6
Conditional Instructions
Whenever I1 is a conditional change of flow instruction e.g. Jcc and
the condition is false, then I2 will be delayed by 1 clock cycle.
6.4.2
Avoiding Program Flow-Control Pipeline
Interlocks
The common way to avoid a flow-control pipeline interlock is to
reorder the code or to use the locations near the end of a Do-Loop
for some other useful instructions.
Note: Some sequences are restricted to be used near the end of a
Do-Loop. Please consult Appendix B of the Family Manual
for details.
The following code is an example of code that was reordered to save
some interlock cycles.
The main loop in the code accumulates elements of an array. If an
element is greater than a threshold, than that value is substracted
from the sum and the number of substracted values is also
calculated.
;straightforward version - 2 interlock cycles in case jump taken (likely case).
;execution time of a single iteration (condition true): 9 clocks
DO
#N,LoopEnd
move
MOTOROLA
Optimizing DSP56300/DSP56600 Applications
X:(r0)+,B;read tested data to B
Program Flow-Control Pipeline Interlocks
Pipeline Interlocks
6-11
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