Table 2-3 Registers Used In Long Addressing - Motorola DSP56600 Manual

Table 2-3 Registers used in Long Addressing

Assembler X
Syntax Field
A10 A1
B10 B1
X X1
Y Y1
A A1
B B1
AB A1
BA B1
Keeping those restrictions in mind, writing a critical data processing
loop efficiently should be done after careful planning of register use
and the data allocations in the memory space according to the
parallelism possible in the calculation at hand. For example, in the
FIR tap calculation given above, the coefficients occupy the X
memory with pointer R0, and the data buffer occupies the Y
memory with pointer R4 (or vice versa). In other cases, the division
may not be so straight forward. For example, in many algorithms
involving complex numbers, the efficient solution uses one memory
space for the real part of the numbers, while the other memory
space is used for the imaginary part. In those examples, there is a
logical separating criterion between the data placed in the X and Y
memories. In many applications, however, variables may be split up
between the X and Y memories based on no other criterion than the
ability to transfer them in parallel to the core at the time they are
called for by the algorithm.
MOTOROLA Optimizing DSP56300/DSP56600 Applications
Shifting/
Y
Limiting if
Field
source
A0 no
B0 no
X0 no
Y0 no
A0 yes
B0 yes
B1 yes
A1 yes
Sign
extension Zero fill if
if destination
destination
no no
no no
no no
no no
A2 no
B2 no
A2,B2 A0,B0
A2,B2 A0,B0
Data Operations
Using the Dual Data Paths
2-5