Addressing Modes - Motorola DSP56156 Manual

INSTRUCTION SET SUMMARY
The Opcode column indicates the Data ALU, AGU, or PCU operation to be performed.
The Operands column specifies the operands to be used by the opcode. The X Bus Data
and G Bus Data columns specify optional data transfers over the X Bus, the G bus and
the addressing modes to be used. The Opcode column must always be included in the
source code.
The DSP offers parallel processing using the Data ALU, AGU, and PCU. For the instruc-
tion word above, the DSP will perform the designated ALU operation (Data ALU), up to
two data transfers specified with address register updates (AGU), and will also decode
the next instruction and fetch an instruction from program memory (PCU) all in one in-
struction cycle. When an instruction is more than one word in length, an additional instruc-
tion execution cycle is required. Most instructions involving the Data ALU are register-
based (all operands are in Data ALU registers) and allow the programmer to keep each
parallel processing unit busy. An instruction which is memory-oriented (such as a bit field
manipulation instruction) or that causes a control flow change (such as a branch/jump)
prevents the use of parallel processing resources during its execution. See the DSP56100
Family Manual for additional information.
1.7.3

Addressing Modes

The addressing modes are grouped into three categories — register direct, address reg-
ister indirect, and special. These addressing modes are summarized in Table 1-11. All ad-
dress calculations are performed in the address generation unit to minimize execution
time. Addressing modes specify whether the operand(s) is(are) in a register, memory, or
encoded in the instruction as immediate data.
The register direct addressing mode can be subclassified according to the specific regis-
ter addressed. The data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0,
A, and B. The control registers include SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.
Address register indirect modes use an address register, Rn, to point to locations in mem-
ory. The content of Rn is the effective address (ea) except in the indexed by offset mode
where the ea is Rn+Nn, or in the indexed by short displacement where the ea is Rn+a
short immediate constant. Address register indirect modes use a modifier register, Mn, to
specify the type of arithmetic to be used to update Rn. If a mode using an offset is speci-
fied, an offset register, Nn, is also used for the update. The Nn and Mn registers are as-
signed to the Rn with the same n. Thus, the assigned register sets are R0;N0;M0,
R1;N1;M1, R2;N2;M2, and R3;N3;M3. This structure is unique and extremely powerful in
general, and particularly powerful in setting up DSP oriented data structures. Two sets of
address registers can be used by the instruction set: one set for the first memory operation
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