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5.9.4
HSR Host Flag 0 (HF0) Bit 3
The Host Flag 0 (HF0) bit indicates the state of Host Flag 0 (HF0) in the Interrupt Control
Register ICR on the host processor side of the host interface. HF0 can only be changed
by the host processor. HF0 is cleared by a DSP reset.
5.9.5
HSR Host Flag 1 (HF1) Bit 4
The Host Flag 1 (HF1) bit indicates the state of Host Flag 1 (HF1) in the Interrupt Control
Register ICR on the host processor side of the host interface. HF1 can only be changed
by the host processor. HF1 is cleared by a DSP reset.
5.9.6
HSR Reserved Status – Bits 5 and 6
These status bits are reserved for future expansion and read as zero during DSP read op-
erations. Reserved bits should be written as zero for future compatibility.
5.9.7
HSR DMA Status (DMA) Bit 7
The DMA status bit (DMA) indicates that the host processor has enabled the DMA mode
of the HI by setting HM1 or HM0 to a one. When the DMA status bit is a zero, it indicates
that the DMA mode is disabled by the Host Mode bits HM0 and HM1(both are cleared) in
the Interrupt Control Register ICR and no DMA operations are pending. When the DMA
status bit is set, the DMA mode is enabled by the Host Mode bits HM0 and HM1. The
channel not in use (i.e., the transmit channel or receive channel) can be used for polled
or interrupt operation by the DSP. DMA is cleared by reset.
5.10
INTERRUPT CONTROL REGISTER (ICR)
The Interrupt Control Register (ICR) is an 8-bit read/write control register used by the host
processor to control the HI interrupts and flags. ICR cannot be accessed by the DSP. ICR
is a read/write register which can be accessed using bit manipulation instructions on con-
trol register bits. The control bits are described in the following paragraphs.
7
6
5
INIT
HM1
HM0
5.10.1 ICR Receive Request Enable (RREQ) Bit 0
The Receive Request enable (RREQ) bit is used to control the HREQ pin for host receive
data transfers. In the Interrupt Mode (DMA off), RREQ is used to enable interrupt requests
via the external Host Request HREQ pin when the Receive Data Register Full (RXDF)
status bit in the Interrupt Status register (ISR) is set. When RREQ is cleared, RXDF inter-
rupts are disabled. When RREQ is set, the external Host Request HREQ pin will be as-
serted if RXDF is set.
5 - 12
INTERRUPT CONTROL REGISTER (ICR)
4
3
2
HF1
HF0
*
TREQ RREQ
HOST INTERFACE
1
0
READ/WRITE
INTERRUPT CONTROL
REGISTER (ICR)
ADDRESS $0
MOTOROLA
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