Address Generation Unit (Agu) - Motorola DSP56156 Manual

X1 X0 Y1 Y0
Figure 1-6 Data ALU Architecture Block Diagram
Saturation arithmetic is provided to selectively limit overflow when reading a data ALU ac-
cumulator register.
The DSP56156 implements two types of rounding: convergent rounding and two's comple-
ment rounding. The type of rounding is selected by the status register rounding bit (R bit).
The logic unit in the MAC array performs the logical operations AND, OR, EOR, and NOT
on data ALU registers. The logic unit is 16 bits wide and operates on data in the MSP por-
tion of the accumulator. The LSP and EXT portions of the accumulator are not affected.
See the DSP56100 Family Manual for additional information.
1.2.4

Address Generation Unit (AGU)

The AGU performs all address storage and effective address calculations necessary to
address data operands in memory (see Figure 1-7). This unit operates in parallel with
other chip resources to minimize address generation overhead. The AGU can imple-
ment three types of arithmetic: linear, modulo, and reverse carry. The Address ALU con-
1 - 10
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
GD(0:15)
L
DXB2(0:15)
DXB1(0:15)
A2 A1 A0 B2 B1
EXA
(0:7)
MSA(0:15)
LSA(0:15)
DSP56156 OVERVIEW
XD(0:15)
S/L
CONDITION
GENERATOR
LSP(0:15)
MSP(0:15)
EXT(0:7)
B0
8
8
ACCUMULATOR
16
16
MUX
16
16
SB(0:15)
NON
MULTIPLY
CONTROL
MR
MULTIPLY -
AND LOGIC
MUX
MOTOROLA