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5.8.6
HCR Reserved Control – Bits 5, 6 and 7
These unused bits are reserved for future expansion and should be written with zeros for
future compatibility.
5.9
HOST STATUS REGISTER (HSR)
The Host Status register (HSR) is an 8-bit read-only status register used by the DSP to
interrogate status and flags of the HI. It cannot be directly accessed by the host processor.
When the HSR register is read to the internal data bus, the register contents occupy the
low order byte of the data bus - the high order portion is zero filled. The status bits are
described in the following paragraphs.
7
6
5
DMA
*
5.9.1
HSR Host Receive Data Full (HRDF) Bit 0
The Host Receive Data Full (HRDF) bit indicates that the Host Receive Data register
(HRX) contains data from the host processor. HRDF is set when data is transferred from
the TXH:TXL registers to the HRX register. HRDF is cleared when the Receive Data reg-
ister HRX is read by the DSP. HRDF can also be cleared by the host processor using the
Initialize function. HRDF is also cleared by a DSP reset. This bit is typically used for polling
operations.
5.9.2
HSR Host Transmit Data Empty (HTDE) Bit 1
The Host Transmit Data Empty (HTDE) bit indicates that the Host Transmit Data register
(HTX) is empty and can be written by the DSP. HTDE is set when the HTX register is
transferred to the RXH:RXL registers. HTDE is cleared when the Transmit Data register
HTX is written by the DSP. HTDE can also be set by the host processor using the Initialize
function. HTDE is also set by a DSP reset. This bit is typically used for polling operations.
5.9.3
HSR Host Command Pending (HCP) Bit 2
The Host Command Pending (HCP) bit indicates that the host processor has set the HC
bit and that a Host Command Interrupt is pending. The HCP bit reflects the status of the
HC bit in the Command Vector Register (CVR) on the host processor side of the host in-
terface. HC and HCP are cleared by the DSP exception hardware when the exception is
taken. The host processor can clear HC which also clears HCP. The HCP is cleared by
DSP reset. This bit is typically used for polling operations.
MOTOROLA
HOST STATUS REGISTER (HSR)
4
3
2
*
HF1
HF0
HCP
HOST INTERFACE
1
0
REGISTER (HSR)
HTDE HRDF
ADDRESS X:$FFE4
READ-ONLY
HOST STATUS
5 - 11
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