Introduction; Timer Architecture; Timer Count Register (Tctr) - Motorola DSP56156 Manual

7.1

INTRODUCTION

This section describes a general purpose 16-bit timer/event counter with internal or exter-
nal clocking which can be used to interrupt the DSP, or to signal an external device at pe-
riodic intervals, after counting internal events, or after counting external events. A Timer
Input pin (TIN) can be used as an event counter input and a Timer Output pin (TOUT) can
be used for timer pulse or timer clock generation. Note that these pins must be enabled
by setting CC10 and CC11 respectively in the Port C Control Register.
7.2

TIMER ARCHITECTURE

Figure 7-1 shows the general block diagram of the timer. It includes three 16-bit registers:
the Timer Count Register (TCTR), the Timer Preload Register (TPR), and the Timer Com-
pare Register (TCPR). An additional Timer Control Register (TCR) controls the timer op-
erations in the Port C Control Register.
A decrement register, programmed by the control register, is not available to the user. All
other registers are read/write registers memory mapped as shown in Figure 7-2.
7.3

TIMER COUNT REGISTER (TCTR)

When the timer is enabled (TE=1), the 16-bit timer count register is decremented by one
after the decrement register has reached the value zero. On the next event after the count
register reaches the value zero, an overflow interrupt will be generated if the Overflow In-
terrupt Enable bit (OIE) is set in the timer control register. Also, the state of the TOUT pin
can then be affected according to the mode selected by the Timer Out Enable bits (TO2-
TO0) of the timer control register. If n is the value stored in the count register when the
timer is enabled, the overflow interrupt occurs after (n+1) * (DC+1) input events, DC being
the preset value of the decrement register. After reaching zero, the count register is re-
loaded with the contents of the preload register or with a direct value if a direct write to the
count register had been executed after the last timer count register reload.
On the next event after the count register reaches the value of the compare register, a
compare interrupt is generated if the Compare Interrupt Enable bit (CIE) is set in the timer
control register. The state of the TOUT pin may also be affected according to the mode
selected by the Timer Out Enable bits (TO2-TO0) of the timer control register.
The user program can write a new value into the count register anytime. If the timer is en-
abled (TE=1) during the write to the count register, this new value is written to the TCTR
on the next count register decrement (next event after the decrement register reaches ze-
ro). If the timer is disabled (TE=0) during the write, the value is immediately written to the
count register and will not be overwritten by the value stored in the preload register when
MOTOROLA

INTRODUCTION

16-BIT TIMER AND EVENT COUNTER 7 - 3