Motorola DSP56156 Manual page 251

SSI OPERATING MODES
Receive Shift Register and transferred to the RX when the corresponding time slot is en-
abled. The DSP will read the receive data register and either use or discard the data ac-
cording to the time slot register and mask.
The frame sync signal indicates the beginning of a new data frame. Each data frame is
divided into time slots and transmission or reception can occur in each time slot (rather
than in just the frame sync time slot as in the normal mode). The frame rate dividers, con-
trolled by DC4, DC3, DC2, DC1, and DC0 control the number of time slots per frame from
2 to 32.
8.19.2.1 Network Mode Transmit
The transmit portion of the SSI is enabled when TE=1. However, when TE is sets the
transmitter will be enabled only after detection of a new data frame sync. This allows the
SSI to synchronize to the network timing.
Normal start up sequence for transmission in the first time slot is to write the data to be
transmitted to the Transmit Register (TX), this clears the TDE flag. Then set TE and TIE
to enable the transmitter on the next frame sync and to enable transmit interrupts.
Alternatively, the DSP programmer may decide not to transmit in the first time slot by writ-
ing (any data) to the Time Slot Register (TSR). This will clear the TDE flag just as if data
were going to be transmitted, but the STD pin will remain in three-state for the first time
slot. The programmer then sets TE and TIE as above.
When the frame sync is detected (or generated), the first enabled data word will be trans-
ferred from TX to the Transmit Shift Register and will be shifted out (transmitted). TX now
being empty will cause TDE to be set which, if TIE is set, will cause a transmitter interrupt.
Software can (1) poll TDE, or (2) use interrupts to reload the TX register with new data for
the next time slot, or (3) write to the TSR to prevent transmitting in the next active time
slot. The transmit and receive slot mask registers control which time slots will be used.
Failing to reload TX (or writing to TSR) before the next active time slot will cause a trans-
mitter underrun and the TUE error bit will be set.
Clearing TE and setting it again will disable the transmitter after completion of transmis-
sion of the current data word until the beginning of the next frame sync period. During that
time the STD pin will be three-stated. TE should be cleared after TDE gets set to ensure
that all pending data is transmitted.
To summarize, the network mode transmitter generates interrupts every enabled time
slot (TE=1, TIE=1) and requires the DSP program to respond to each enabled time slot.
These responses may be:
8 - 26 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1) MOTOROLA