Motorola DSP56156 Manual page 239

Table 8-2 SSI Bit Clock as a Function of Fosc and PM0-PM7 (PSR=0)
Fosc Max bit
Clock
(MHz) (MHz)
16.384 4.096
18.432 4.608
20.480 5.12
26.624 6.656
24.576 6.144
24.704 6.176
32.768 8.192
36.864 9.216
49.152 12.288
49.408 12.352
65.536 16.384
73.728 18.432
Examples:
in 8-bit word network mode: DC0-DC4= 26, PM0-PM7=8, PSR=0, Fosc =
62.22MHz would give a bit clock of 62.22Mhz ÷ [4x9] = 1.728 kHz for a 27 slot TDM
multiplex of 8-bit words. The sampling rate for every word (FS rate) would then be
1.728 kHz ÷ [27x8] = 8kHz.
in 8-bit word normal mode: DC0-DC4= 1, PM0-PM7=9, PSR=1, Fosc =
40.96MHz would give a bit clock of 40.96Mhz ÷ [8x4x10] = 128 kHz. The 8-bit word
rate being equal to 2, the sampling rate (FS rate) would then be 128 kHz ÷ [2x8] =
8kHz.
A divide ratio of one (DC=00000) in network mode is a special case. In normal mode, a
divide ratio of one (DC=00000) provides continuous periodic data word transfer. Note that
a 1-bit sync (FSL=1) must be used in this case.
Note: The frame divider control bits have to be written before the first three serial clock
cycles of the last slot of a frame in order to become active at the beginning of the
next frame.
8.11.3 CRA Word Length Control (WL0,WL1) Bits 13, 14
The Word Length Control bits are used to select the length of the data words being trans-
ferred via the SSI. Word lengths of 8, 12, or 16 bits may be selected as shown in Table
8-3.
8 - 14 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI CONTROL REGISTER A (CRA)
PM0-PM7 Values for different SCK
2.048MHz 1.544MHz
1 -
- -
- -
- -
2 -
- 3
3 -
- -
5 -
- 7
7 -
8 -
1.536MHz 128KHz
- 31($1F)
2 35($23)
- 39($27)
- 51($33)
3 47($2F)
- -
- 63($3F)
5 71($47)
7 95($5F)
- -
- 127($7F)
- 143($8F)
64KHz
63($3F)
71($47)
79($4F)
103($67)
95($5F)
-
127($7F)
143(8F)
191($BF)
-
255($FF)
-
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