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3.1.1.1
X Data Memory
The on-chip X data RAM is a 16-bit-wide, internal, static memory occupying the lowest
2048 locations (0–$7FF) in X memory space. The on-chip peripheral registers occupy the
top 64 locations of the X data memory ($FFC0–$FFFF). The On-Chip X Data Memory ad-
dresses are received from the X address Bus one (XAB1) and X address Bus two (XAB2)
and data transfers occur on the X data bus (XDB) and global data bus (GDB). Two reads,
one read, or one write can be performed during one instruction cycle on the internal data
memory. The on-chip peripherals occupy the top 64 locations in the X data memory space
(X:$FFC0-X:$FFFF). X memory may be expanded off-chip for a total of 65,536 address-
able locations.
3.1.1.2
Program Memory
On-chip program memory consists of a 2048-location by 16-bit, high-speed RAM that is
enabled/disabled by the MA and MB bits in the OMR. The On-Chip Program Memory ad-
dresses are received from the program control logic (usually the program counter) or from
the address ALU on the PAB. Off-chip program memory may be written using move pro-
gram memory (MOVEM) instructions. The first 64 locations of the program memory
($0000–$003F) are reserved for interrupt vectors. The program memory may be expand-
ed off-chip for a total of 65,536 addressable locations.
3.1.1.3
Bootstrap Memory
A 64-location program bootstrap ROM is only read by the program controller while in the
bootstrap mode, during which, the on-chip program RAM is defined as write-only. The
bootstrap program can load from any one of three different sources. Selection of which
one of the three is made by reading the mode pins and, if necessary, bit-15 of P:$C000
from the external data bus.
If MB:MA = 00 (Mode 0) then the bootstrap program will load from an external byte-wide
memory. This bootstrap program will load 4,096 bytes from the external P: memory space
beginning at location P:$C000 (bits 0-7). These will be packed into 2,048 16-bit words and
stored in contiguous internal program RAM memory locations starting at P:$0000. The
byte-wide data will be packed into the 16-bit memory least significant byte first.
If MB:MA = 01 (Mode 1), the bootstrap program will read bit-15 of P:$C000 from the ex-
ternal data bus. If bit-15 = 0, the bootstrap program will load 4,096 bytes through the host
port (the host processor can terminate down-loading early by setting HF0=0). If bit-15 = 1,
the bootstrap program will load through SSI0. Data is packed into program RAM least sig-
nificant byte of P:$0000 first.
3 - 4
OPERATING MODES AND MEMORY SPACES
RAM MEMORY DESCRIPTION
MOTOROLA
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