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3.1.1.4.2
Bootstrap Mode (Mode 1)
Mode 1 is one of two bootstrap modes which have all internal program and data RAM
memories enabled (see Figure 3-1). This mode can be entered by either grounding the
MB pin and pulling the MA pin high or by writing to the OMR and changing the MA and
MB bits (see Table 3-1). When the operating mode is first changed to Mode 1, the
DSP56156 executes a bootstrap program which loads program memory from either the
host port or SSI0 depending on whether bit 15 of location P:C000 is a zero (host port) or
a one (SSI0). Section 3.1.2.2 describes the bootstrap operation. The memory maps for
Mode 0 and Mode 1 are identical. The difference between Mode 0 and Mode 2 is the lo-
cation of the reset vector in program memory. The reset vector location in Mode 0 is at
internal memory location P:$0000. The reset vector location in Mode 2 is at external mem-
ory location P:$E000.
3.1.1.4.3
Normal Expanded Mode (Mode 2)
The normal expanded mode (Mode 2) has the same memory map as Mode 0 and Mode
1 (see Figure 3-1). The difference is that entering Mode 2 does not cause the bootstrap
program to be executed and the reset vectors to external program memory location
P:$C000. This mode can be entered by either grounding the MA pin and pulling the MB
pin high or by writing to the OMR and changing the MA and MB bits (see Table 3-1).
3.1.1.4.4
Development Mode (Mode 3)
The development mode is similar to the normal expanded mode except that internal pro-
gram memory is disabled (see Figure 3-1). All references to program memory space are
directed to external program memory, which is accessed on the external data bus. This
mode can be entered by either pulling the MA and MB pins high or by writing to the OMR
and changing the MA and MB bits (see Table 3-1). DSP56156ROM chips with bad or ob-
solete internal program ROM code can be used with external program memory in the
development mode. Reset vectors to external program memory location P:$0000. Boot-
strap Mode
3.1.2
Bootstrap Mode
The bootstrap feature consists of a special on-chip bootstrap ROM containing a bootstrap
program and a bootstrap control logic. The bootstrap feature is only available on the pro-
gram RAM part. It is not available on the program ROM part. Appendix A describes the
contents of the boot ROM.
3.1.2.1
Bootstrap ROM
This 64-word on-chip ROM is factory programmed to perform the actual bootstrap operation
from the memory expansion port (Port A), from the Host Interface, or from the Synchronous
3 - 6
OPERATING MODES AND MEMORY SPACES
RAM MEMORY DESCRIPTION
MOTOROLA
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