Motorola DSP56156 Manual page 65

ing of the clock which sampled BB high. The BR output signal will remain as-
serted until the DSP no longer needs the bus. In this mode, the Request Hold
bit (RH) of the Bus Control Register (BCR) allows BR to be asserted under soft-
ware control.
During external accesses caused by an instruction executed out of external
program memory, BR remains asserted low for consecutive external X memory
accesses and continues toggling for consecutive external P memory accesses
unless the Request Hold bit (RH) is set inside the Bus Control Register (BCR).
In the master mode, BR can also be used for non arbitration purpose: if BG is
always asserted, BR is asserted in t0 of every external bus access. It can then
be used as a chip select to turn a external memory device off and on between
internal and external bus accesses. BR timing is in that case similar to A0-A15,
R/W and PS/DS; it is asserted and deasserted during t0.
BG (Bus Grant) - active low input when in master mode, active low output
when in slave mode. Output after power on reset if the slave is selected, this
pin is asserted to acknowledge an external bus request. It indicates that the
DSP will release control of the external address bus A0-A15, data bus D0-D15
and bus control pins when BB is deasserted. The BG output is asserted in re-
sponse to a BR input. When the BG output is asserted and BB is deasserted,
the external address bus A0-A15, data bus D0-D15 and bus control pins are
in the high impedance state. BG assertion may occur in the middle of an in-
struction which requires more than one external bus cycle for execution. Note
that BG assertion will not occur during indivisible read-modify-write instruc-
tions (BFSET, BFCLR, BFCHG). When BR is deasserted, the BG output is
deasserted and the DSP regains control of the external address bus, data bus,
and bus control pins when the BB pin is sampled high.
This pin becomes an input if the master bit in the OMR register is set (Master
Mode). It is asserted by an external processor when the DSP may become the
bus master. The DSP can start normal external memory access after the BB pin
has been deasserted by the previous bus master. When BG is deasserted, the
DSP will release the bus as soon as the current transfer is completed. The state
of BG may be tested by testing the BS bit in the Bus Control Register.
BG is ignored during hardware reset.
BB (Bus Busy) - active low input when not bus master, active low output
when bus master. This pin is asserted by the DSP when it becomes the bus
master and it performs an external access. It is deasserted when the DSP re-
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BUS CONTROL (9 PINS)
DSP56156 PIN DESCRIPTIONS MOTOROLA