Ssix Interface Programming Model - Motorola DSP56156 Manual

which configures all I/O pins as general purpose input. The SSI will re-
main in the reset state while all SSI pins are programmed as general pur-
pose I/O (CC0-CC4/CC5-CC9 cleared) and will become active only
when at least one of the SSIx I/O pins is programmed as NOT general
purpose I/O. All status and control bits in the SSIx are affected as de-
scribed below.
SSIx Reset The SSIx personal reset is generated when CC0-CC4/CC5-CC9 bits are
cleared. This returns the SSIx pins to general purpose I/O pins. The SSIx
status bits are preset to the same state produced by the DSP reset; how-
ever, the SSIx control bits are unaffected. The SSIx personal reset is use-
ful for selective reset of the SSIx interface without changing the present
SSIx control bits setup and without affecting the other peripherals.
STOP Reset The STOP reset is caused by executing the STOP instruction. During the
STOP state no clocks are active in the chip. The SSI status bits are preset
to the same state produced by the DSP reset. The SSI control bits are un-
affected. The SSI pins remain defined as SSIx pins. The STOP reset con-
dition is like the personal reset condition except that the SSI pins do not
revert to general purpose I/O pins.
The correct sequence to initialize the SSI interface is as follows:
1. DSP reset or SSIx reset
2. Program SSIx control registers
3. Configure SSIx pins (at least one) as not general purpose I/O
The DSP programmer should use the DSP or SSIx reset before changing the MOD, SYN,
FSI, FSL, MSB, SCKP, SCKD, FSD1, A/MU, FSD0 control bits to ensure proper operation
of the SSIx interface. That is, these control bits should not be changed during SSIx oper-
ation.
Note: The SSIx clock must go low for at least four complete periods to ensure proper SSIx
reset.
8.6

SSIx INTERFACE PROGRAMMING MODEL

The registers comprising the SSI interface are shown in Figure 8-8. Note that standard
Codec devices label the Most Significant Bit as bit 0, whereas the DSP labels the LSB as
bit 0. Therefore, when using a standard Codec (requiring LSB first), the SHFD bit in the
CRB should be cleared (MSB first).
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)

SSIx INTERFACE PROGRAMMING MODEL

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