Tcr Timer Enable (Te) Bit 15; Timer Resolution; Functional Description Of The Timer - Motorola DSP56156 Manual

inverted and the decrement register is decremented on all 0 to 1 transitions. INV is cleared
on hardware RESET and software reset (RESET instruction).
7.6.7

TCR Timer Enable (TE) Bit 15

The TE bit is used to enable or disable the timer. Setting the TE bit will enable the timer.
The decrement register will start decrementing from its preset value each time an event
comes in. Clearing the TE bit will disable the timer. The decrement register will be preset
to the value contained in bits DC7-DC0 of the control register, and the count register will
be loaded with the value of the preload register. However, if a direct write to the count reg-
ister has happened since the last count register reload, the value written will be loaded
into the count register instead of the preload value. TE is cleared by hardware RESET and
software reset (RESET instruction).
7.7

TIMER RESOLUTION

Table 7-2 shows the range of timer interrupt rate (overflow interrupt using internal event,
Fosc/2) that is provided by the 16-bit count register, the 16-bit preload register and the 8-
bit decrement register in combination. The overflow interrupt occurs every (PRE-
LOAD+1)*(DC7-DC0+1) input clock cycles.
ICycle Time
33 ns
(60MHz-30 MIPS)
51 ns
(39 MHz-19.5MIPS))
74 ns
(27 MHz-13.5MIPS)
7.8

FUNCTIONAL DESCRIPTION OF THE TIMER

The figures given in this section illustrate most configurations in which the timer can be
enabled, disabled and used.
7 - 8

TIMER RESOLUTION

Table 7-2 Timer Range and Resolution
DC7-DC0 value
0
255
0
255
0
255
16-BIT TIMER AND EVENT COUNTER
Interrupt Rate
(Preload = 2 16 )
2.162 ms
553.5 ms
3.342 ms
855.6 ms
4.85 ms
1.242 s
Resolution
(Preload=0)
33 ns
8.4 µs
51 ns
13.06 µs
74 ns
18.94 µs
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