Motorola DSP56156 Manual page 261

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PLCR
DSP core phase PH0 is put on the CLCKO pin. PH0 is a delayed version of the DSP
core master clock Fosc. Fext or Fext/2 (Fext being a squared and delayed version of the
signal applied to the EXTAL input pin) can also be selected on CLCKO by changing
CS1-CS0 according to Table 9-1
9.3.4 GSM Bit (GSM) Bit 12
This bit is used to select the on-chip codec clock. When the GSM bit is cleared, the out-
put of the four bit divider ED3-ED0 is selected as the on-chip codec clock. When this bit
is set, the clock applied to EXTAL is divided by 6.5 and selected for the codec clock. The
status of this bit does not affect the input clock of the on-chip PLL. Like all COCR bits,
the GSM bit is cleared by the DSP hardware reset and is not affected by software reset.
9.3.5 PLCR PLL Power Down Bit (PLLD) Bit 13
When the PLLD bit is set, the on-chip PLL is put in the power down mode and stops
operating. When this control bit is cleared, the on-chip PLL is turned on. This bit cannot
be set when the PLLE bit is set.
Since the STOP instruction does not power down the PLL, if the PLL has to be turned off
before entering the stop mode, the following sequence will have to be executed before
the STOP instruction:
• clear the PLLE bit (switch back to EXTAL)
• set the PLLD bit (power down the PLL)
• execute the STOP instruction
Setting the PLLD bit clears the LOCK bit.
9.3.6 PLCR PLL Enable Bit (PLLE) Bit 14
When the PLLE bit is set, the DSP core system clock is generated by the on-chip PLL.
When this control bit is cleared, the external frequency applied to the EXTAL pin is used
as the system clock for the core, by-passing the PLL. The PLL state is defined by the
PLLD bit: when the PLLD bit is set, the PLL is in the power down mode and when the
PLLD bit is cleared, the PLL is in the active mode. Table 9-2 summarizes the function of
PLLE and PLLD.
9 - 8
Table 9-1 CLKOUT Pin Control
CS1 CS0
0 0
0 1
1 0
1 1
ON-CHIP FREQUENCY SYNTHESIZER
CLKOUT
PH0
reserved
Squared Fext
Squared Fext/2
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