Motorola DSP56156 Manual page 256

9.1 INTRODUCTION
The PLL performs frequency multiplication to allow the processor to use almost any
available external system clock for full speed operation, while also supplying an output
clock synchronized to a synthesized internal core clock. It improves the synchronous tim-
ing of the processor's external memory port, eliminating the timing skew common on
other processors.
The PLL's ability to operate at a high internal frequency using a low frequency input
offers two immediate benefits. Lower frequency inputs reduce the overall electromag-
netic interference generated by a system, and the ability to oscillate at different frequen-
cies reduces costs by eliminating the need to add additional oscillators to a system.
This PLL is strictly used for generating clocks in the DSP and is not intended to lock on a
signal to be processed. The basic operation of the PLL is as follows. The phase compar-
ator compares its two inputs and generates an difference signal which is integrated by
the filter. The filter output is used to control the voltage controlled oscillator (VCO) which,
if the VCO is fed directly into the phase comparator, forms a closed negative feedback
loop that will cause the VCO to oscillate at the same phase and frequency as the input
clock. If the output of the VCO is divided by n before being fed to the phase comparator,
then the VCO must oscillate at n times the input clock rate so that the output of the
divider which is fed to the phase comparator is the same frequency and phase as the
input clock.
The DSP56156 does not contain an on-chip oscillator. An external system clock must be
connected to the EXTAL pin. Figure 9-1 shows the on-chip frequency synthesizer gen-
eral block diagram.This clock, after being squared, can be divided on-chip by a four bit
divider and used as master clock for the codec block and for the on-chip phase-locked
loop (PLL) block. The codec input clock can also be sourced by a fixed, input clock
divided by 6.5, signal. The PLL generates the DSP core system clock but can also be
bypassed allowing the core to directly use the clock provided on the EXTAL pin.
Note: This Section replaces the PLL description in the DSP56100 Family Manual for the
DSP56156. There are some differences in the control registers for the PLL for the
DSP56156 that are unique to this part.
9.1.1 PLL Components
The PLL block diagram is shown in Figure 9-1. The components of the PLL are described
in the following sections and a programming model summary (Figure 9-3) is at the end of
the section.
9.1.1.1 Phase Comparator and Filter
The Phase Comparator detects any phase difference between the external clock and an
MOTOROLA
INTRODUCTION
ON-CHIP FREQUENCY SYNTHESIZER 9 - 3