Port Registers; Bus Control Register (Bcr) - Motorola DSP56156 Manual

I/O PORT SET-UP AND PROGRAMMING
Ports B and C pins may be programmed under software control as general purpose I/O pins
or as dedicated on-chip peripheral pins. A Port Control Register is associated with each
port which allows the port pins to be selected for one of these two functions. All port B pins
are collectively configured as general purpose I/O pins if the corresponding Port Control
Register bit is cleared and all are configured as HI pins if the corresponding Port Control
Register bit is set. In contrast, each Port C pin is independently configured as a general pur-
pose I/O pin if the corresponding Port Control Register bit is cleared and is configured as
an SSI or timer pin if the corresponding Port Control Register bit is set. If a port pin is se-
lected as a general purpose I/O pin, the direction of that pin is determined by a correspond-
ing control bit in the Port Data Direction Register. The port pin is configured as an input if
the corresponding Data Direction Register bit is cleared and is configured as an output if
the corresponding Data Direction Register bit is set. All Port Control Register bits and Data
Direction Register bits are cleared on processor reset, configuring all port pins as general
purpose input pins. If the port pin is selected as an on-chip peripheral pin, the correspond-
ing data direction bit is ignored and the direction of that pin is determined by the operating
mode of the on-chip peripheral.
A port pin configured as a general purpose I/O pin is accessed through an associated Port
Data Register B or C. Data written to the Port Data Register is stored in an output latch.
If the port pin is configured as an output, the output latch data is driven out on the port pin.
When the Port Data Register is read, the logic value on the output port pin is read. If the
port pin is configured as an input, data written to the Port Data Register is still stored in
the output latch but is not gated to the port pin. When the Port Data Register is read, the
state of the port pin is read. That is, reading the port data register will reflect the state of
the pins regardless of how they were configured.
When a port pin is configured as a dedicated on-chip peripheral pin, the port data register
will read the state of the input pin or output driver.
4.2.1

Port Registers

Ports A, B and C are controlled by programmable registers. Port A is controlled by the Bus
Control Register which controls memory wait states and ports B and C each have regis-
ters that select the peripheral to be available and control of that peripheral.
4.2.1.1

Bus Control Register (BCR)

Port A Bus Control Register (BCR) is a 16-bit read/write register. It can be programmed
to insert waits states in a bus cycle during external memory accesses. 5 bit wait control
fields specify between 0 and 31 wait states for an external X memory and P memory ac-
cess. Wait state fields are set to $1F during hardware reset.
4 - 4 I/O INTERFACE MOTOROLA