Crb Sync/Async (Syn) Bit 10; Crb Ssi Mode Select (Mod) Bit 11 - Motorola DSP56156 Manual

8.12.10

CRB Sync/Async (SYN) Bit 10

The Sync/Async control bit controls whether receive and transmit functions of the SSI oc-
cur synchronously or asynchronously with respect to each other. When SYN is cleared,
asynchronous mode is chosen and separate frame sync signals are used for the transmit
and receive sections. When SYN is set, synchronous mode is chosen and the transmit
and receive sections use common clock and frame sync signals.
8.12.11

CRB SSI Mode Select (MOD) Bit 11

The Mode select bit selects the operational mode of the SSI. When MOD is cleared, the
normal mode is selected. When MOD is set, the network mode is selected.
8.12.12 CRB SSI Transmit Enable (TE) Bit 12
The SSI Transmit Enable bit enables the transfer of data from the TX register to the Trans-
mit Shift Register. When TE is set and a frame sync is detected, the transmit portion of
the SSI is enabled. When TE is cleared, the transmitter will be disabled after completing
transmission of data currently in the SSI Transmit Shift Register.The serial output is then
three-stated and any data present in TX will not be transmitted; i.e., data can be written
to TX with TE cleared, TDE will get cleared but data will not be transferred to the Transmit
Shift Register.
Normal transmit enable sequence for transmit is to write data to TX or to TSR before set-
ting TE. Normal transmit disable sequence is to clear TE and TIE after TDE=1.
In the network mode, the operation of clearing TE and setting it again will disable the
transmitter after completion of transmission of a current data word until the beginning of
a new data frame period. During the disabled time period, the STD pin will remain in
three-state.
Note: TE does not inhibit TDE or transmitter interrupts. TE does not affect the generation
of frame sync.
8.12.13 CRB SSI Receive Enable (RE) Bit 13
When the SSI Receive Enable bit is set, the receive portion of the SSI is enabled. When
this bit is cleared, the receiver will be disabled by inhibiting data transfer into RX. If data
is being received while this bit is cleared, the rest of the word will be shifted in and trans-
ferred to the SSI Receive Data Register.
In network mode, the operation of clearing RE and setting it again will disable the receiver
after reception of the current data word until the beginning of the new data frame.
Note: RE does not inhibit RDF or receiver interrupts. RE does not affect the generation
of a frame sync.
8 - 18 SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
SSI CONTROL REGISTER B (CRB)
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