Motorola DSP56156 Manual page 35

Table 1-5 Exception Priorities within an IPL
Priority
Highest Hardware
Illegal Instruction Interrupt
Lowest
Highest IRQA (External Interrupt)
IRQB (External Interrupt)
Host Command Interrupt
Host/DMA RX Data Interrupt
Host/DMA TX Data Interrupt
SSI0 RX Data with
Exception Status
SSI0 TX Data with
Exception Status
SSI1 RX Data with
Exception Status
SSI1 TX Data with
Exception Status
Timer Overflow Interrupt
Lowest Timer Compare Interrupt
1 - 14
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
Exception
Level 3 (Non-maskable)
RESET
Stack Error
SWI
Level 0, 1, 2 (Maskable)
CODEC
SSI0 RX Data
SSI0 TX Data
SSI1 RX Data
SSI1 TX Data
DSP56156 OVERVIEW
IP Reg.
Enabled by
Bit No.
— —
— —
— —
IRQA
0, 1
mode bits
3, 4
IRQB
mode bits
COIE 6,7
HCIE 2
HRIE 0
HTIE 1
RIE 15
RIE 15
TIE 14
TIE 14
RIE 15
RIE 15
TIE 14
TIE 14
OIE 9
CIE 10
Control
Register
Address
—
—
—
X:$FFDF
X:$FFDF
X:$FFDF
X:$FFC4
X:$FFC4
X:$FFC4
X:$FFD1
X:$FFD1
X:$FFD1
X:$FFD1
X:$FFD9
X:$FFD9
X:$FFD9
X:$FFD9
X:$FFEC
X:$FFEC
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