Cvr Host Command Bit (Hc) Bit 7; Host Control Register (Hcr) - Motorola DSP56156 Manual

INTERRUPT SOURCE
RECEIVE DATA FULL
TRANSMIT DATA EMPTY
HOST COMMAND
5.7.3

CVR Host Command Bit (HC) Bit 7

The Host Command bit (HC) is used by the host to handshake the execution of host com-
mand exceptions. Normally the host processor sets HC=1 to request the host command
exception from the DSP. When the host command exception is taken by the DSP, the HC
bit is cleared by the HI hardware. The host processor can read the state of HC to deter-
mine when execution of the host command has started. The host processor may elect to
clear the HC bit, cancelling the Host Command Exception request at any time before it is
recognized by the DSP.
The command exception might be recognized by the DSP and
executed before it can be canceled by the host, even if the
host clears the HC bit.
Setting HC causes HCP (Host Command Pending) to be set in the HSR register. The host
can write HC and HV in the same write cycle if desired. HC is cleared by DSP reset.
5.8

HOST CONTROL REGISTER (HCR)

The Host Control Register (HCR) is an 8-bit read/write control register used by the DSP
to control the HI interrupts and flags. HCR cannot be accessed by the host processor. The
HCR register occupies the low order byte of the internal data bus - the high order portion
MOTOROLA

HOST CONTROL REGISTER (HCR)

Table 5-1 Host Interface Interrupt Structure
DSP INTERRUPT STRUCTURE
STATUS
HRDF
HTDE
HCP
HOST PROCESSOR HREQ STRUCTURE
HREQ SOURCE
RECEIVE DATA FULL
TRANSMIT DATA EMPTY
CAUTION:
HOST INTERFACE
MASK EXCEPTION STARTING
ADDRESS
HRIE $0028
HTIE $002A
HCIE 2*HV($0000-003E)
STATUS MASK
RXDF RREQ
TXDE TREQ
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