Data Buses; Address Buses - Motorola DSP56156 Manual

Clock & Control
XAB1
XAB2
PAB
PDB
GDB
XDB
BITFIELD UNIT
1.2.1

Data Buses

Data movement on the chip occurs over three bidirectional 16-bit buses: the X Data Bus
(XDB), the Program Data Bus (PDB), and the Global Data Bus (GDB). Data transfer be-
tween the Data ALU and the X Data Memory occurs over the XDB when one memory ac-
cess is performed, over the XDB and the GDB when two simultaneous memory reads are
performed. All other data transfers occur over the Global Data Bus. Instruction word pre-
fetches take place in parallel over the PDB. The bus structure supports general register
to register, register to memory, memory to register, and memory to memory data move-
ment and can transfer up to three 16-bit words in the same instruction cycle.
1.2.2

Address Buses

Addresses are specified for internal X Data Memory on two unidirectional 16-bit buses —
X Address Bus One (XAB1) and X Address Bus Two (XAB2). Program memory address-
es are specified on the PAB. External memory spaces are addressed via a single 16-bit,
unidirectional address bus driven by a three input multiplexer that can select the XAB1,
1 - 8
DSP56100 CORE BLOCK DIAGRAM DESCRIPTION
OMR SR
INSTR DECODER
and
LA LC
INTERRUPT UNIT
SP PC
SSH SSL
PROGRAM
CONTROLLER
LIMITER
IBS
and
Y1 Y0 X1 X0
OnCE
Figure 1-5 DSP56100 CORE Block Diagram
DSP56156 OVERVIEW
M0 N0 R0
M1 N1 R1
MOD.
ALU
ALU
M2 N2 R2
M3 N3 R3
ADR ALU
CLOCK
GEN.
SHIFTER/LIMITER
DATA
ALU
A2 A1 A0 B2 B1 B0
MAC
and
ALU
MOTOROLA