Motorola DSP56156 Manual page 13

Figure
Number
1-1 DSP56100 Family Product Literature . . . . . . . . . . . . . . . . . . . . 1-3
1-2 Detailed RAM Based Part Block Diagram . . . . . . . . . . . . . . . . . . 1-5
1-3 Detailed ROM Based Part Block Diagram . . . . . . . . . . . . . . . . . . 1-6
1-4 DSP56156 RAM and ROM Based Functional Block Diagram . . . . . . . . 1-6
1-5 DSP56100 CORE Block Diagram . . . . . . . . . . . . . . . . . . . . . . 1-7
1-6 Data ALU Architecture Block Diagram . . . . . . . . . . . . . . . . . . . . 1-9
1-7 AGU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1-8 Interrupt Priority Register IPR (Address X:$FFDF) . . . . . . . . . . . . . 1-11
1-9 Input/Output Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1-10 DSP56156 Programming Model . . . . . . . . . . . . . . . . . . . . . . . 1-20
1-11 Status Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1-12 Operating Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
2-1 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2-2 DSP56156 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
2-3 TA Controlled Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
3-1 DSP56156 RAM Memory Map . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3-2 DSP56156 ROM Memory Map
4-1 DSP56156 Input / Output Block Diagram . . . . . . . . . . . . . . . . . . 4-5
4-2 I/O Port B and C Programming Models . . . . . . . . . . . . . . . . . . . 4-7
4-3 DSP56156 On-chip peripherals Memory Map . . . . . . . . . . . . . . . . 4-8
5-1 Host Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-2 Host Interface - DSP Programming Model . . . . . . . . . . . . . . . . . . 5-6
5-3 Host Interface - Host Processor Programming Model . . . . . . . . . . . . 5-8
6-1 DSP56156 On-chip Sigma/Delta Functional Diagram . . . . . . . . . . . . 6-3
6-2 DSP56156 Analog Input and Output Diagram . . . . . . . . . . . . . . . . 6-5
6-3 On-Chip Codec Programming Model . . . . . . . . . . . . . . . . . . . . 6-6
6-4 Log Magnitude Frequency Response of the
A/D Comb Filter for F=2.048 MHz and D=128 . . . . . . . . . . . . . . . . 6-13
6-5 Log Magnitude Frequency Response of the
A/D Comb Filter in the 0-4 KHz Band for F=2.048 MHz and D=128 . . . . . 6-14
MOTOROLA
Revision 2.1
LIST of FIGURES
Title
SECTION 1
SECTION 2
SECTION 3
. . . . . . . . . . . . . . . . . . . . . . . 3-9
SECTION 4
SECTION 5
SECTION 6
LIST of FIGURES
DSP56004 DESIGN SPECIFICATION
Page
Number
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