Hcr Host Receive Interrupt Enable (Hrie) Bit 0; Hcr Host Transmit Interrupt Enable (Htie) Bit 1; Hcr Host Command Interrupt Enable (Hcie) Bit 2; Hcr Host Flag 3 (Hf3) Bit 4 - Motorola DSP56156 Manual

is zero filled. HCR is a read/write register which can be accessed using bit manipulation
instructions on control register bits. Any reserved bits are read as zeros and should be
programmed as zeros for future compatibility. The contents of HCR are cleared on DSP
reset. The control bits are described in the following paragraphs.
7 6 5
* *
5.8.1

HCR Host Receive Interrupt Enable (HRIE) Bit 0

The Host Receive Interrupt Enable (HRIE) bit is used to enable a DSP interrupt when the
Host Receive Data Full (HRDF) status bit in the Host Status register (HSR) is set. When
HRIE is cleared, HRDF interrupts are disabled. When HRIE is set, a Host Receive Data
interrupt request will occur if HRDF is set.
5.8.2

HCR Host Transmit Interrupt Enable (HTIE) Bit 1

The Host Transmit Interrupt Enable (HTIE) bit is used to enable a DSP interrupt when the
Host Transmit Data Empty (HTDE) status bit in the Host Status Register (HSR) is set.
When HTIE is cleared, HTDE interrupts are disabled. When HTIE is set, a Host Transmit
Data interrupt request will occur if HTDE is set.
5.8.3

HCR Host Command Interrupt Enable (HCIE) Bit 2

The Host Command Interrupt Enable (HCIE) bit is used to enable a vectored DSP inter-
rupt when the Host Command Pending (HCP) status bit in the Host Status Register (HSR)
is set. When HCIE is cleared, HCP interrupts are disabled. When HCIE is set, a Host
Command interrupt request will occur if HCP is set. The starting address of this interrupt
is determined by the Host Vector (HV).
5.8.4 HCR Host Flag 2 (HF2) Bit 3
The Host Flag 2 (HF2) bit is used as a general purpose flag for DSP to host processor
communication. Changing HF2 will change the Host Flag 2 (HF2) bit of the Interrupt Sta-
tus Register ISR on the host processor side of the host interface. HF2 may be set or
cleared by the DSP.
5.8.5

HCR Host Flag 3 (HF3) Bit 4

The Host Flag 3 (HF3) bit is used as a general purpose flag for DSP to host processor
communication. Changing HF3 will change the Host Flag 3 (HF3) bit of the Interrupt Sta-
tus Register ISR on the host processor side of the host interface. HF3 may be set or
cleared by the DSP.
5 - 10
HOST CONTROL REGISTER (HCR)
4 3 2
* HF3 HF2 HCIE
HOST INTERFACE
1 0
HOST CONTROL
HTIE HRIE REGISTER (HCR);
ADDRESS X:$FFC4
READ/WRITE
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