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INTERRUPT STATUS REGISTER (ISR)
5.11
INTERRUPT STATUS REGISTER (ISR)
The Interrupt Status register (ISR) is an 8-bit read-only status register used by the host
processor to interrogate the status and flags of the HI. The ISR can not be accessed by
the DSP. The status bits are described in the following paragraphs.
READ-ONLY
7
6
5
4
3
2
1
0
INTERRUPT STATUS
REGISTER (ISR)
HREQ DMA
*
HF3
HF2
TRDY TXDE RXDF
ADDRESS $2
5.11.1 ISR Receive Data Register Full (RXDF) Bit 0
The Receive Data Register Full (RXDF) bit indicates that both the Receive Byte Registers,
RXH and RXL, contain data from the DSP and may be read by the host processor. RXDF
is set when the contents of the Host Transmit Data Register HTX is transferred to the Re-
ceive Byte Registers RXH:RXL. RXDF is cleared when the Receive Data Low (RXL) reg-
ister is read by the host processor. RXL is normally the last byte of the Receive Byte Reg-
isters to be read by the host processor. RXDF can be cleared by the host processor using
the Initialize function. RXDF is cleared by a DSP reset. RXDF may be used to assert the
external Host Request HREQ pin if the Receive Request enable RREQ bit is set. RXDF
provides valid status regardless of whether the RXDF interrupt is enabled or not so that
polling techniques may be used by the host processor.
5.11.2 ISR Transmit Data Register Empty (TXDE) Bit 1
The Transmit Data Register Empty (TXDE) bit indicates that the Transmit Byte Registers
TXH and TXL are both empty and can be written by the host processor. TXDE is set when
the content of the Transmit Byte Registers TXH:TXL are transferred to the Host Receive
Data Register (HRX). TXDE is cleared when the Transmit Byte Low (TXL) register is writ-
ten by the host processor. TXL is normally the last byte of the Transmit Byte Registers to
be written by the host processor. TXDE can be set by the host processor using the Initial-
ize feature. TXDE is set by a DSP reset. TXDE may be used to assert the external Host
Request HREQ pin if the Transmit Request Enable TREQ bit is set. TXDE provides valid
status regardless of whether the TXDE interrupt is enabled or not so that polling tech-
niques may be used by the host.
5.11.3 ISR Transmitter Ready (TRDY) Bit 2
The Transmitter Ready (TRDY) status bit indicates that both the Transmit Byte Registers
and Host Receive Data register are empty, i.e., the channel from the host processor
through the HI to the DSP CPU is clear. By testing TRDY, the host processor programmer
can be assured that the first word received by the DSP will be the first word the host pro-
cessor transmits.
5 - 16
HOST INTERFACE
MOTOROLA
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