Motorola DSP56156 Manual page 99

7 6
INIT HM1 HM0
7 6
HC *
7 6
HREQ DMA
7 6
IV7 IV6 IV5
15
RXH (ADDR $6)
HIGH BYTE
15
TXH (ADDR $6)
HIGH BYTE
ADDR (BIN)
HA2 HA1 HA0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Figure 5-3 Host Interface - Host Processor Programming Model
5 - 8
COMMAND VECTOR REGISTER (CVR)
5 4 3 2
HF1 HF0
5 4 3 2
* HV
5 4 3 2
* HF3 HF2 TRDY TXDE RXDF
5 4 3 2
IV4 IV3 IV2
8 7
RXL (ADDR $7)
LOW BYTE
8 7
TXL (ADDR $7)
LOW BYTE
HOST READ
ICR(8 BIT)
CVR (8 BIT)
ISR (8 BIT)
IVR (8 BIT)
read zeros
reserved
RXH (8 BIT)
RXL (8 BIT)
HOST INTERFACE
1 0
* TREQ RREQ
1 0
1 0
1 0
IV1 IV0
0
0
HOST WRITE
ICR (8 BIT)
CVR (8 BIT)
not used
IVR (8 BIT)
not used
reserved
TXH (8 BIT)
TXL (8 BIT)
READ/WRITE
INTERRUPT CONTROL
REGISTER (ICR);
ADDRESS $0
READ/WRITE
COMMAND VECTOR
REGISTER (CVR);
ADDRESS $1
READ-ONLY
INTERRUPT STATUS
REGISTER (ISR);
ADDRESS $2
READ/WRITE
INTERRUPT VECTOR
REGISTER (IVR);
ADDRESS $3
READ-ONLY
RECEIVE BYTE
REGISTERS;
ADDRESSES $6,7
WRITE-ONLY
TRANSMIT BYTE
REGISTERS;
ADDRESSES $6,7
HOST INTERFACE
HOST PROCESSOR
ADDRESS MAP
MOTOROLA