Motorola DSP56156 Manual page 169

6.6.4 Example 4
This example illustrates an application where the input clock provided on the EXTAL pin is
9.72 MHz and where the final sampling rate of the data converted is expected to be 8 KHz.
The different clock synthesis and decimation/interpolation ratios for the Σ∆ A/D and D/A
sections are shown in Figure 6-33.
PLL Block
9.72MHz
EXTAL
Codec Block
2nd order
Σ∆ modulator
1 bit
D/A
Figure 6-33 Example 4 functional block diagram
6 - 54
APPLICATION EXAMPLES
1.944MHz
÷
x 1,..., x16
5
1.944MHz
1.944MHz
2nd order
digital
Σ∆ modulator
÷
486KHz
3 pole
2 zero
LPF
5dB
DSP56156 ON-CHIP SIGMA/DELTA CODEC
x 4
24KHz
÷
81
81:1
3rd order
Comb Filter
24KHz
1:81
2nd order
Comb Filter
4
1.944MHz
4:1
3rd order
Comb Filter
DSP Core
Fosc
3:1
decimation
8 KHz
and
16-bit
compensation
sample
filter
1:3
interpolation
8 KHz
and
16-bit
compensation
sample
filter
MOTOROLA