Motorola DSP56156 Manual page 26

DSP56100 Family Features
• Up to 30 Million Instructions per Second (MIPS) at
60 MHz.– 33.3 ns Instruction cycle
• Single-cycle 16 x 16-bit parallel Multiply-
Accumulate
• 2 x 40-bit accumulators with extension byte
• Fractional and integer arithmetic with support for
multiprecision arithmetic
• Highly parallel instruction set with unique DSP
addressing modes
• Nested hardware DO loops including infinite loops
and DO zero loop
• Two instruction LMS adaptive filter loop
• Fast auto-return interrupts
• Two external interrupt request pins
DSP56156 On-chip Resources — RAM Version
• 2K x 16 on-chip data RAM
• 2K x 16 on-chip program RAM
• One bootstrap ROM
• Bootstrap loading from external byte wide PROM,
Host Interface, or Synchronous Serial Interface 0
(SSI0)
• One external 16-bit address bus
• One external 16-bit data bus
• On-chip peripheral registers memory mapped in
data memory space
• On-chip Σ∆ voice band codec (A/D-D/A)
– Internal voltage reference
– No off-chip components required
DSP56156ROM On-chip Resources
• 2K x 16 on-chip data RAM
• 8K x 16 on-chip program ROM
• One external 16-bit address bus
• One external 16-bit data bus
• On-chip peripheral registers memory mapped in
data memory space
• On-chip Σ∆ voice band codec (A/D-D/A)
– No off-chip components required
Operational Differences of the ROM Based Part from the RAM Based Part
• PROM area
P:$2F00 — P:$2FFF is reserved and should not
be programmed or accessed by the user
MOTOROLA
INTRODUCTION
• Three 16-bit internal data and three 16-bit internal
address buses
• Individual programmable wait states on the
external bus for program, and data
• On-chip memory-mapped peripheral registers
• Low Power Wait and Stop modes
• On-Chip Emulation (OnCE) for unobtrusive,
processor speed independent debugging
• Operating frequency down to DC
• 5V single power supply
• Low power (HCMOS)
• 27 general purpose I/O pins
• On-chip, programmable, frequency synthesizer
(PLL)
• Byte-wide Host Interface with DMA support
• Two independent synchronous serial interfaces
– built in µ-law and A-law compression/expansion
– up to 32 software selectable time slots in
network mode
• One 16-bit timer
• 112 pin quad flat pack packaging
– Internal voltage reference (2/5 of positive power
supply)
• 27 general purpose I/O pins
• On-chip, programmable PLL
• Byte-wide Host Interface with DMA support
• Two independent synchronous serial interfaces
• One 16-bit timer
• 112 pin quad flat pack packaging
DSP56156 OVERVIEW 1 - 5